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[/] [open8_urisc/] [trunk/] [VHDL/] [hd44780_4b.vhd] - Diff between revs 287 and 322

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Rev 287 Rev 322
Line 36... Line 36...
  use ieee.std_logic_arith.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_misc.all;
  use ieee.std_logic_misc.all;
 
 
entity hd44780_4b is
entity hd44780_4b is
generic(
generic(
  Tsu                        : integer :=  40; -- ns
  Tas                        : integer :=   40; -- ns
  Tpw                        : integer := 250; -- nS
  Tpwe                       : integer :=  250; -- nS
  Tcyc                       : integer := 500; -- nS
  Tcyce                      : integer := 1000; -- nS
  Clock_Frequency            : real    := 50000000.0; -- Hz
  Clock_Frequency            : real    := 100000000.0; -- Hz
  Reset_Level                : std_logic := '1'
  Reset_Level                : std_logic := '1'
);
);
port(
port(
  Clock                      : in  std_logic;
  Clock                      : in  std_logic;
  Reset                      : in  std_logic;
  Reset                      : in  std_logic;
Line 75... Line 75...
    return retval;
    return retval;
  end function;
  end function;
 
 
  constant CONV_NANOSECS     : real := 0.000000001;
  constant CONV_NANOSECS     : real := 0.000000001;
 
 
  constant Tsu_r             : real := CONV_NANOSECS * real(Tsu);
  constant Tas_r             : real := CONV_NANOSECS * real(Tas);
  constant Tpw_r             : real := CONV_NANOSECS * real(Tpw);
  constant Tpwe_r            : real := CONV_NANOSECS * real(Tpwe + Tas);
  constant Tcyc_r            : real := CONV_NANOSECS * real(Tcyc);
  constant Tcyc_r            : real := CONV_NANOSECS * real(Tcyce + Tas);
 
 
  constant TCYC_i            : integer := integer(Clock_Frequency * Tcyc_r);
  constant TCYC_i            : integer := integer(Clock_Frequency * Tcyc_r);
  constant TCYC_BITS         : integer := ceil_log2(TCYC_i);
  constant TCYC_BITS         : integer := ceil_log2(TCYC_i);
 
 
  constant TCYC_DELAY        : std_logic_vector(TCYC_BITS-1 downto 0) :=
  constant TCYC_DELAY        : std_logic_vector(TCYC_BITS-1 downto 0) :=
                               conv_std_logic_vector(TCYC_i-1, TCYC_BITS);
                               conv_std_logic_vector(TCYC_i-1, TCYC_BITS);
  signal tcyc_timer          : std_logic_vector(TCYC_BITS - 1 downto 0) :=
 
                               (others => '0');
 
 
 
  constant TPW_i             : integer := integer(Clock_Frequency * Tpw_r);
  constant TAS_i             : integer := integer(Clock_Frequency * Tas_r);
  constant TPW_DELAY         : std_logic_vector(TCYC_BITS-1 downto 0) :=
  constant TAS_DELAY         : std_logic_vector(TCYC_BITS - 1 downto 0) :=
                               conv_std_logic_vector(TPW_i-1, TCYC_BITS);
                               conv_std_logic_vector(TAS_i-1,TCYC_BITS);
 
 
  constant TSU_i             : integer := integer(Clock_Frequency * Tsu_r);
  constant TPWE_i            : integer := integer(Clock_Frequency * Tpwe_r);
  constant TSU_BITS          : integer := ceil_log2(TSU_i);
  constant TPWE_DELAY        : std_logic_vector(TCYC_BITS-1 downto 0) :=
  constant TSU_DELAY         : std_logic_vector(TSU_BITS - 1 downto 0) :=
                               conv_std_logic_vector(TPWE_i-1, TCYC_BITS);
                               conv_std_logic_vector(TSU_i-1,TSU_BITS);
 
  signal tsnh_timer          : std_logic_vector(TSU_BITS-1 downto 0) :=
  signal tcyc_timer          : std_logic_vector(TCYC_BITS - 1 downto 0) :=
                                (others => '0');
                                (others => '0');
 
 
  type IO_STATES   is (IDLE,
  type IO_STATES   is (IDLE,
                       INIT_UB, TAS_UB, TPW_UB, TCYC_UB,
                       TAS_UB, TPW_UB, TCYC_UB,
                       INIT_LB, TPW_LB, TCYC_LB,
                       INIT_LB, TPW_LB, TCYC_LB,
                       DONE );
                       DONE );
  signal io_state            : IO_STATES;
  signal io_state            : IO_STATES;
  signal fn_set              : std_logic;
  signal fn_set              : std_logic;
 
 
Line 121... Line 119...
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      io_state               <= IDLE;
      io_state               <= IDLE;
      fn_set                 <= '0';
      fn_set                 <= '0';
      tcyc_timer             <= (others => '0');
      tcyc_timer             <= (others => '0');
      tsnh_timer             <= (others => '0');
 
      Wr_Buffer              <= (others => '0');
      Wr_Buffer              <= (others => '0');
      IO_Done                <= '0';
      IO_Done                <= '0';
      LCD_RS                 <= '0';
      LCD_RS                 <= '0';
      LCD_E                  <= '0';
      LCD_E                  <= '0';
      LCD_DQ                 <= (others => '0');
      LCD_DQ                 <= (others => '0');
    elsif( rising_edge(Clock) )then
    elsif( rising_edge(Clock) )then
      IO_Done                <= '0';
      IO_Done                <= '0';
 
      LCD_RS                 <= '0';
      LCD_E                  <= '0';
      LCD_E                  <= '0';
 
      LCD_DQ_U               <= (others => '0');
      LCD_DQ_L               <= (others => '0');
      LCD_DQ_L               <= (others => '0');
 
      tcyc_timer             <= tcyc_timer + 1;
 
 
      case( io_state )is
      case( io_state )is
        when IDLE =>
        when IDLE =>
 
          tcyc_timer         <= (others => '0');
          if( Wr_En = '1' )then
          if( Wr_En = '1' )then
            Wr_Buffer        <= Wr_Reg & Wr_Data;
            Wr_Buffer        <= Wr_Reg & Wr_Data;
            fn_set           <= Wr_Fnset;
            fn_set           <= Wr_Fnset;
            io_state         <= INIT_UB;
 
          end if;
 
 
 
        when INIT_UB =>
 
          tsnh_timer         <= TSU_DELAY;
 
          tcyc_timer         <= (others => '0');
 
          LCD_RS             <= Wr_Buffer_A;
 
          io_state           <= TAS_UB;
          io_state           <= TAS_UB;
 
          end if;
 
 
        when TAS_UB =>
        when TAS_UB =>
          tsnh_timer         <= tsnh_timer - 1;
          LCD_RS             <= Wr_Buffer_A;
          if( or_reduce(tsnh_timer) = '0' )then
          if( tcyc_timer >= TAS_DELAY )then
            io_state         <= TPW_UB;
            io_state         <= TPW_UB;
          end if;
          end if;
 
 
        when TPW_UB =>
        when TPW_UB =>
          tcyc_timer         <= tcyc_timer + 1;
          LCD_RS             <= Wr_Buffer_A;
          LCD_E              <= '1';
          LCD_E              <= '1';
          LCD_DQ_U           <= Wr_Buffer_U;
          LCD_DQ_U           <= Wr_Buffer_U;
          if( tcyc_timer = TPW_DELAY )then
          if( tcyc_timer >= TPWE_DELAY )then
            io_state         <= TCYC_UB;
            io_state         <= TCYC_UB;
          end if;
          end if;
 
 
        when TCYC_UB =>
        when TCYC_UB =>
          tcyc_timer         <= tcyc_timer + 1;
          LCD_RS             <= Wr_Buffer_A;
 
          LCD_DQ_U           <= Wr_Buffer_U;
          if( tcyc_timer >= TCYC_DELAY )then
          if( tcyc_timer >= TCYC_DELAY )then
            io_state         <= INIT_LB;
            io_state         <= INIT_LB;
          end if;
          end if;
 
 
        when INIT_LB =>
        when INIT_LB =>
          tcyc_timer         <= (others => '0');
          tcyc_timer         <= TAS_DELAY;
 
          LCD_RS             <= Wr_Buffer_A;
 
          LCD_DQ_U           <= Wr_Buffer_U;
          io_state           <= TPW_LB;
          io_state           <= TPW_LB;
          if( fn_set = '1' )then
          if( fn_set = '1' )then
            fn_set           <= '0';
            fn_set           <= '0';
            io_state         <= TPW_UB;
            io_state         <= TPW_UB;
          end if;
          end if;
 
 
        when TPW_LB =>
        when TPW_LB =>
          tcyc_timer         <= tcyc_timer + 1;
          LCD_RS             <= Wr_Buffer_A;
          LCD_E              <= '1';
          LCD_E              <= '1';
          LCD_DQ_U           <= Wr_Buffer_L;
          LCD_DQ_U           <= Wr_Buffer_L;
          if( tcyc_timer = TPW_DELAY )then
          if( tcyc_timer >= TPWE_DELAY )then
            io_state         <= TCYC_LB;
            io_state         <= TCYC_LB;
          end if;
          end if;
 
 
        when TCYC_LB =>
        when TCYC_LB =>
          tcyc_timer         <= tcyc_timer + 1;
          LCD_RS             <= Wr_Buffer_A;
 
          LCD_DQ_U           <= Wr_Buffer_L;
          if( tcyc_timer >= TCYC_DELAY )then
          if( tcyc_timer >= TCYC_DELAY )then
            io_state         <= DONE;
 
          end if;
 
 
 
        when DONE =>
 
          IO_Done            <= '1';
          IO_Done            <= '1';
          LCD_RS             <= '0';
 
          LCD_DQ_U           <= (others => '0');
 
          io_state           <= IDLE;
          io_state           <= IDLE;
 
          end if;
 
 
        when others =>
        when others =>
          null;
          null;
      end case;
      end case;
    end if;
    end if;

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