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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
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entity hd44780_4b is
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entity hd44780_4b is
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generic(
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generic(
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Tsu : integer := 40; -- ns
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Tas : integer := 40; -- ns
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Tpw : integer := 250; -- nS
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Tpwe : integer := 250; -- nS
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Tcyc : integer := 500; -- nS
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Tcyce : integer := 1000; -- nS
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Clock_Frequency : real := 50000000.0; -- Hz
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Clock_Frequency : real := 100000000.0; -- Hz
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Reset_Level : std_logic := '1'
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Reset_Level : std_logic := '1'
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);
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);
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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Line 75... |
return retval;
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return retval;
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end function;
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end function;
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constant CONV_NANOSECS : real := 0.000000001;
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constant CONV_NANOSECS : real := 0.000000001;
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constant Tsu_r : real := CONV_NANOSECS * real(Tsu);
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constant Tas_r : real := CONV_NANOSECS * real(Tas);
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constant Tpw_r : real := CONV_NANOSECS * real(Tpw);
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constant Tpwe_r : real := CONV_NANOSECS * real(Tpwe + Tas);
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constant Tcyc_r : real := CONV_NANOSECS * real(Tcyc);
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constant Tcyc_r : real := CONV_NANOSECS * real(Tcyce + Tas);
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constant TCYC_i : integer := integer(Clock_Frequency * Tcyc_r);
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constant TCYC_i : integer := integer(Clock_Frequency * Tcyc_r);
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constant TCYC_BITS : integer := ceil_log2(TCYC_i);
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constant TCYC_BITS : integer := ceil_log2(TCYC_i);
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constant TCYC_DELAY : std_logic_vector(TCYC_BITS-1 downto 0) :=
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constant TCYC_DELAY : std_logic_vector(TCYC_BITS-1 downto 0) :=
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conv_std_logic_vector(TCYC_i-1, TCYC_BITS);
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conv_std_logic_vector(TCYC_i-1, TCYC_BITS);
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signal tcyc_timer : std_logic_vector(TCYC_BITS - 1 downto 0) :=
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(others => '0');
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constant TPW_i : integer := integer(Clock_Frequency * Tpw_r);
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constant TAS_i : integer := integer(Clock_Frequency * Tas_r);
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constant TPW_DELAY : std_logic_vector(TCYC_BITS-1 downto 0) :=
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constant TAS_DELAY : std_logic_vector(TCYC_BITS - 1 downto 0) :=
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conv_std_logic_vector(TPW_i-1, TCYC_BITS);
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conv_std_logic_vector(TAS_i-1,TCYC_BITS);
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constant TSU_i : integer := integer(Clock_Frequency * Tsu_r);
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constant TPWE_i : integer := integer(Clock_Frequency * Tpwe_r);
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constant TSU_BITS : integer := ceil_log2(TSU_i);
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constant TPWE_DELAY : std_logic_vector(TCYC_BITS-1 downto 0) :=
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constant TSU_DELAY : std_logic_vector(TSU_BITS - 1 downto 0) :=
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conv_std_logic_vector(TPWE_i-1, TCYC_BITS);
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conv_std_logic_vector(TSU_i-1,TSU_BITS);
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signal tsnh_timer : std_logic_vector(TSU_BITS-1 downto 0) :=
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signal tcyc_timer : std_logic_vector(TCYC_BITS - 1 downto 0) :=
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(others => '0');
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(others => '0');
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type IO_STATES is (IDLE,
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type IO_STATES is (IDLE,
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INIT_UB, TAS_UB, TPW_UB, TCYC_UB,
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TAS_UB, TPW_UB, TCYC_UB,
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INIT_LB, TPW_LB, TCYC_LB,
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INIT_LB, TPW_LB, TCYC_LB,
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DONE );
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DONE );
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signal io_state : IO_STATES;
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signal io_state : IO_STATES;
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signal fn_set : std_logic;
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signal fn_set : std_logic;
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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io_state <= IDLE;
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io_state <= IDLE;
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fn_set <= '0';
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fn_set <= '0';
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tcyc_timer <= (others => '0');
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tcyc_timer <= (others => '0');
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tsnh_timer <= (others => '0');
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Wr_Buffer <= (others => '0');
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Wr_Buffer <= (others => '0');
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IO_Done <= '0';
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IO_Done <= '0';
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LCD_RS <= '0';
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LCD_RS <= '0';
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LCD_E <= '0';
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LCD_E <= '0';
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LCD_DQ <= (others => '0');
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LCD_DQ <= (others => '0');
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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IO_Done <= '0';
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IO_Done <= '0';
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LCD_RS <= '0';
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LCD_E <= '0';
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LCD_E <= '0';
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LCD_DQ_U <= (others => '0');
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LCD_DQ_L <= (others => '0');
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LCD_DQ_L <= (others => '0');
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tcyc_timer <= tcyc_timer + 1;
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case( io_state )is
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case( io_state )is
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when IDLE =>
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when IDLE =>
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tcyc_timer <= (others => '0');
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if( Wr_En = '1' )then
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if( Wr_En = '1' )then
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Wr_Buffer <= Wr_Reg & Wr_Data;
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Wr_Buffer <= Wr_Reg & Wr_Data;
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fn_set <= Wr_Fnset;
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fn_set <= Wr_Fnset;
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io_state <= INIT_UB;
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end if;
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when INIT_UB =>
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tsnh_timer <= TSU_DELAY;
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tcyc_timer <= (others => '0');
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LCD_RS <= Wr_Buffer_A;
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io_state <= TAS_UB;
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io_state <= TAS_UB;
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end if;
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when TAS_UB =>
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when TAS_UB =>
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tsnh_timer <= tsnh_timer - 1;
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LCD_RS <= Wr_Buffer_A;
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if( or_reduce(tsnh_timer) = '0' )then
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if( tcyc_timer >= TAS_DELAY )then
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io_state <= TPW_UB;
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io_state <= TPW_UB;
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end if;
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end if;
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when TPW_UB =>
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when TPW_UB =>
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tcyc_timer <= tcyc_timer + 1;
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LCD_RS <= Wr_Buffer_A;
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LCD_E <= '1';
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LCD_E <= '1';
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LCD_DQ_U <= Wr_Buffer_U;
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LCD_DQ_U <= Wr_Buffer_U;
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if( tcyc_timer = TPW_DELAY )then
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if( tcyc_timer >= TPWE_DELAY )then
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io_state <= TCYC_UB;
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io_state <= TCYC_UB;
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end if;
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end if;
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when TCYC_UB =>
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when TCYC_UB =>
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tcyc_timer <= tcyc_timer + 1;
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LCD_RS <= Wr_Buffer_A;
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LCD_DQ_U <= Wr_Buffer_U;
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if( tcyc_timer >= TCYC_DELAY )then
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if( tcyc_timer >= TCYC_DELAY )then
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io_state <= INIT_LB;
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io_state <= INIT_LB;
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end if;
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end if;
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when INIT_LB =>
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when INIT_LB =>
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tcyc_timer <= (others => '0');
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tcyc_timer <= TAS_DELAY;
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LCD_RS <= Wr_Buffer_A;
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LCD_DQ_U <= Wr_Buffer_U;
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io_state <= TPW_LB;
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io_state <= TPW_LB;
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if( fn_set = '1' )then
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if( fn_set = '1' )then
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fn_set <= '0';
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fn_set <= '0';
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io_state <= TPW_UB;
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io_state <= TPW_UB;
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end if;
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end if;
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when TPW_LB =>
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when TPW_LB =>
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tcyc_timer <= tcyc_timer + 1;
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LCD_RS <= Wr_Buffer_A;
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LCD_E <= '1';
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LCD_E <= '1';
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LCD_DQ_U <= Wr_Buffer_L;
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LCD_DQ_U <= Wr_Buffer_L;
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if( tcyc_timer = TPW_DELAY )then
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if( tcyc_timer >= TPWE_DELAY )then
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io_state <= TCYC_LB;
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io_state <= TCYC_LB;
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end if;
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end if;
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when TCYC_LB =>
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when TCYC_LB =>
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tcyc_timer <= tcyc_timer + 1;
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LCD_RS <= Wr_Buffer_A;
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LCD_DQ_U <= Wr_Buffer_L;
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if( tcyc_timer >= TCYC_DELAY )then
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if( tcyc_timer >= TCYC_DELAY )then
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io_state <= DONE;
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end if;
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when DONE =>
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IO_Done <= '1';
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IO_Done <= '1';
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LCD_RS <= '0';
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LCD_DQ_U <= (others => '0');
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io_state <= IDLE;
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io_state <= IDLE;
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end if;
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end if;
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end if;
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