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--
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--
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-- VHDL Entity: o8_hd44780_if
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-- VHDL Entity: o8_hd44780_if
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-- Description: Provides low-level timing of the control signals in 8-bit mode
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-- Description: Provides low-level timing of the control signals in 8-bit mode
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-- (required by o8_hd44780_if)
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-- (required by o8_hd44780_if)
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--
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--
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-- Note: This code attempts to implement the timing diagram in the HD44780U
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-- LCD II datasheet with a few simplifications. Chiefly, DQ is updated
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-- at the start of E, rather than attempting to assert within Tds of
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-- the falling edge of E. Further, both RS and DQ are asserted until
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-- the end of Tcycle, where Tcycle is defined as TcycleE + Tas
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 04/12/21 Design Start
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-- Seth Henry 04/12/21 Design Start
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-- Seth Henry 09/19/23 Rewrote IF to use a single cycle timer
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
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entity hd44780_8b is
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entity hd44780_8b is
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generic(
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generic(
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Tsu : integer := 40; -- ns
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Tas : integer := 50; -- ns
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Tpw : integer := 250; -- nS
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Tpwe : integer := 450; -- ns
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Tcyc : integer := 500; -- nS
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Tcyce : integer := 1000; -- ns
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Clock_Frequency : real := 50000000.0; -- Hz
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Clock_Frequency : real := 100000000.0; -- Hz
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Reset_Level : std_logic := '1'
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Reset_Level : std_logic := '1'
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);
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);
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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return retval;
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return retval;
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end function;
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end function;
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constant CONV_NANOSECS : real := 0.000000001;
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constant CONV_NANOSECS : real := 0.000000001;
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constant Tsu_r : real := CONV_NANOSECS * real(Tsu);
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constant Tas_r : real := CONV_NANOSECS * real(Tas);
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constant Tpw_r : real := CONV_NANOSECS * real(Tpw);
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constant Tpwe_r : real := CONV_NANOSECS * real(Tpwe + Tas);
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constant Tcyc_r : real := CONV_NANOSECS * real(Tcyc);
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constant Tcyc_r : real := CONV_NANOSECS * real(Tcyce + Tas);
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constant TCYC_i : integer := integer(Clock_Frequency * Tcyc_r);
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constant TCYC_i : integer := integer(Clock_Frequency * Tcyc_r);
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constant TCYC_BITS : integer := ceil_log2(TCYC_i);
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constant TCYC_BITS : integer := ceil_log2(TCYC_i);
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constant TCYC_DELAY : std_logic_vector(TCYC_BITS-1 downto 0) :=
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constant TCYC_DELAY : std_logic_vector(TCYC_BITS-1 downto 0) :=
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conv_std_logic_vector(TCYC_i-1, TCYC_BITS);
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conv_std_logic_vector(TCYC_i-1, TCYC_BITS);
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signal tcyc_timer : std_logic_vector(TCYC_BITS - 1 downto 0) :=
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signal tcyc_timer : std_logic_vector(TCYC_BITS - 1 downto 0) :=
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(others => '0');
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(others => '0');
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constant TPW_i : integer := integer(Clock_Frequency * Tpw_r);
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constant TAS_i : integer := integer(Clock_Frequency * Tas_r);
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constant TPW_DELAY : std_logic_vector(TCYC_BITS-1 downto 0) :=
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constant TAS_DELAY : std_logic_vector(TCYC_BITS - 1 downto 0) :=
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conv_std_logic_vector(TPW_i-1, TCYC_BITS);
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conv_std_logic_vector(TAS_i-1,TCYC_BITS);
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constant TSU_i : integer := integer(Clock_Frequency * Tsu_r);
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constant TPWE_i : integer := integer(Clock_Frequency * Tpwe_r);
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constant TSU_BITS : integer := ceil_log2(TSU_i);
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constant TPWE_DELAY : std_logic_vector(TCYC_BITS-1 downto 0) :=
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constant TSU_DELAY : std_logic_vector(TSU_BITS - 1 downto 0) :=
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conv_std_logic_vector(TPWE_i-1, TCYC_BITS);
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conv_std_logic_vector(TSU_i-1,TSU_BITS);
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signal tsnh_timer : std_logic_vector(TSU_BITS-1 downto 0) :=
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(others => '0');
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type IO_STATES is (IDLE, INIT, IO_TAS, IO_TPW, IO_TCYC, DONE );
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type IO_STATES is (IDLE, IO_TAS, IO_TPWE, IO_TCYC );
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signal io_state : IO_STATES;
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signal io_state : IO_STATES;
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signal Wr_Buffer : std_logic_vector(8 downto 0);
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signal Wr_Buffer : std_logic_vector(8 downto 0);
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alias Wr_Buffer_A is Wr_Buffer(8);
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alias Wr_Buffer_A is Wr_Buffer(8);
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alias Wr_Buffer_D is Wr_Buffer(7 downto 0);
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alias Wr_Buffer_D is Wr_Buffer(7 downto 0);
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LCD_IO_proc: process( Clock, Reset )
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LCD_IO_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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io_state <= IDLE;
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io_state <= IDLE;
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tcyc_timer <= (others => '0');
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tcyc_timer <= (others => '0');
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tsnh_timer <= (others => '0');
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Wr_Buffer <= (others => '0');
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Wr_Buffer <= (others => '0');
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IO_Done <= '0';
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IO_Done <= '0';
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LCD_RS <= '0';
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LCD_RS <= '0';
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LCD_E <= '0';
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LCD_E <= '0';
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LCD_DQ <= (others => '0');
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LCD_DQ <= (others => '0');
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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IO_Done <= '0';
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IO_Done <= '0';
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LCD_RS <= '0';
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LCD_E <= '0';
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LCD_E <= '0';
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LCD_DQ <= x"00";
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tcyc_timer <= tcyc_timer + 1;
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case( io_state )is
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case( io_state )is
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when IDLE =>
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when IDLE =>
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tcyc_timer <= (others => '0');
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if( Wr_En = '1' )then
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if( Wr_En = '1' )then
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Wr_Buffer <= Wr_Reg & Wr_Data;
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Wr_Buffer <= Wr_Reg & Wr_Data;
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io_state <= INIT;
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end if;
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when INIT =>
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tsnh_timer <= TSU_DELAY;
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tcyc_timer <= (others => '0');
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LCD_RS <= Wr_Buffer_A;
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io_state <= IO_TAS;
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io_state <= IO_TAS;
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end if;
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when IO_TAS =>
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when IO_TAS =>
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tsnh_timer <= tsnh_timer - 1;
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LCD_RS <= Wr_Buffer_A;
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if( or_reduce(tsnh_timer) = '0' )then
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if( tcyc_timer >= TAS_DELAY )then
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io_state <= IO_TPW;
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io_state <= IO_TPWE;
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end if;
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end if;
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when IO_TPW =>
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when IO_TPWE =>
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tcyc_timer <= tcyc_timer + 1;
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LCD_RS <= Wr_Buffer_A;
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LCD_E <= '1';
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LCD_E <= '1';
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LCD_DQ <= Wr_Buffer_D;
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LCD_DQ <= Wr_Buffer_D;
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if( tcyc_timer = TPW_DELAY )then
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if( tcyc_timer >= TPWE_DELAY )then
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io_state <= IO_TCYC;
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io_state <= IO_TCYC;
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end if;
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end if;
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when IO_TCYC =>
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when IO_TCYC =>
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tcyc_timer <= tcyc_timer + 1;
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LCD_RS <= Wr_Buffer_A;
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LCD_DQ <= Wr_Buffer_D;
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if( tcyc_timer >= TCYC_DELAY )then
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if( tcyc_timer >= TCYC_DELAY )then
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io_state <= DONE;
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end if;
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when DONE =>
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IO_Done <= '1';
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IO_Done <= '1';
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LCD_RS <= '0';
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LCD_DQ <= (others => '0');
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io_state <= IDLE;
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io_state <= IDLE;
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end if;
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end if;
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end if;
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