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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_7seg.vhd] - Diff between revs 241 and 244

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Rev 241 Rev 244
Line 33... Line 33...
--
--
-- Revision History
-- Revision History
-- Author          Date     Change
-- Author          Date     Change
------------------ -------- ---------------------------------------------------
------------------ -------- ---------------------------------------------------
-- Seth Henry      05/08/19 Design Start
-- Seth Henry      05/08/19 Design Start
 
-- Seth Henry      05/18/20 Added write qualification input
 
 
library ieee;
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_arith.all;
Line 54... Line 55...
  Common_Cathode             : boolean   := TRUE;
  Common_Cathode             : boolean   := TRUE;
  Address                    : ADDRESS_TYPE
  Address                    : ADDRESS_TYPE
);
);
port(
port(
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
 
  Write_Qual                 : in  std_logic := '1';
  Rd_Data                    : out DATA_TYPE;
  Rd_Data                    : out DATA_TYPE;
  --
  --
  SegLED1                    : out std_logic_vector(6 downto  0);
  SegLED1                    : out std_logic_vector(6 downto  0);
  SegLED2                    : out std_logic_vector(6 downto  0)
  SegLED2                    : out std_logic_vector(6 downto  0)
);
);
Line 70... Line 72...
 
 
  constant User_Addr         : std_logic_vector(15 downto 2)
  constant User_Addr         : std_logic_vector(15 downto 2)
                               := Address(15 downto 2);
                               := Address(15 downto 2);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
  signal Addr_Match          : std_logic;
  signal Addr_Match          : std_logic;
  alias  Reg_Addr            is Open8_Bus.Address(1 downto 0);
 
  signal Reg_Sel             : std_logic_vector(1 downto 0);
  alias  Reg_Sel_d           is Open8_Bus.Address(1 downto 0);
  signal Wr_En               : std_logic;
  signal Reg_Sel_q           : std_logic_vector(1 downto 0) := "00";
  signal Wr_Data_q           : DATA_TYPE;
  signal Wr_En_d             : std_logic := '0';
  signal Rd_En               : std_logic;
  signal Wr_En_q             : std_logic := '0';
 
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
 
  signal Wr_Data_q           : DATA_TYPE := x"00";
 
  signal Rd_En_d             : std_logic := '0';
 
  signal Rd_En_q             : std_logic := '0';
 
 
  signal LED1_Reg            : std_logic_vector(4 downto 0);
  signal LED1_Reg            : std_logic_vector(4 downto 0);
  signal LED1_Brt            : DATA_TYPE;
  signal LED1_Brt            : DATA_TYPE;
  signal LED2_Reg            : std_logic_vector(4 downto 0);
  signal LED2_Reg            : std_logic_vector(4 downto 0);
  signal LED2_Brt            : DATA_TYPE;
  signal LED2_Brt            : DATA_TYPE;
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                                 );
                                 );
 
 
begin
begin
 
 
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
 
  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
 
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
 
 
  io_reg: process( Clock, Reset )
  io_reg: process( Clock, Reset )
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      Reg_Sel                <= "00";
      Reg_Sel_q              <= "00";
      Wr_En                  <= '0';
      Wr_En_q                <= '0';
      Wr_Data_q              <= x"00";
      Wr_Data_q              <= x"00";
 
      Rd_En_q                <= '0';
 
      Rd_Data                <= OPEN8_NULLBUS;
 
 
      LED1_Reg               <= Default_LED1_Value;
      LED1_Reg               <= Default_LED1_Value;
      LED2_Reg               <= Default_LED2_Value;
      LED2_Reg               <= Default_LED2_Value;
      LED1_Brt               <= Default_LED1_Bright;
      LED1_Brt               <= Default_LED1_Bright;
      LED2_Brt               <= Default_LED2_Bright;
      LED2_Brt               <= Default_LED2_Bright;
      Rd_En                  <= '0';
 
      Rd_Data                <= OPEN8_NULLBUS;
 
    elsif( rising_edge( Clock ) )then
    elsif( rising_edge( Clock ) )then
      Reg_Sel                <= Reg_Addr;
      Reg_Sel_q              <= Reg_Sel_d;
 
 
      Wr_En                  <= Addr_Match and Open8_Bus.Wr_En;
      Wr_En_q                <= Wr_En_d;
      Wr_Data_q              <= Open8_Bus.Wr_Data;
      Wr_Data_q              <= Wr_Data_d;
      if( Wr_En = '1' )then
      if( Wr_En_q = '1' )then
        case( Reg_Sel )is
        case( Reg_Sel_q )is
          when "00" =>
          when "00" =>
            LED1_Reg         <= Wr_Data_q(4 downto 0);
            LED1_Reg         <= Wr_Data_q(4 downto 0);
          when "01" =>
          when "01" =>
            LED2_Reg         <= Wr_Data_q(4 downto 0);
            LED2_Reg         <= Wr_Data_q(4 downto 0);
          when "10" =>
          when "10" =>
Line 176... Line 185...
          when others =>
          when others =>
            null;
            null;
        end case;
        end case;
      end if;
      end if;
 
 
 
      Rd_En_q                <= Rd_En_d;
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_En                  <= Addr_Match and Open8_Bus.Rd_En;
 
      if( Rd_En = '1' )then
      if( Rd_En = '1' )then
        case( Reg_Sel )is
        case( Reg_Sel_q )is
          when "00" =>
          when "00" =>
            Rd_Data          <= "000" & LED1_Reg;
            Rd_Data          <= "000" & LED1_Reg;
          when "01" =>
          when "01" =>
            Rd_Data          <= "000" & LED2_Reg;
            Rd_Data          <= "000" & LED2_Reg;
          when "10" =>
          when "10" =>

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