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-- Copyright (c)2013 Jeremy Seth Henry
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-- Copyright (c)2006, 2015, 2020 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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| Line 27... |
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--
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--
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-- Notes : All output registers are updated by writing an instruction to
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-- Notes : All output registers are updated by writing an instruction to
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-- : offset 0x1F.
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-- : offset 0x1F.
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-- : The math unit is busy when the MSB of the status
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-- : The math unit is busy when the MSB of the status
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-- : register is high, and done/ready when it reads low.
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-- : register is high, and done/ready when it reads low.
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-- : Almost Equal checks to see if Addend 1 is no more, or less
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-- : Almost Equal checks to see if Addend 1 is no more, or less,
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-- : addend 2 within the specified tolerance. For example,
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-- : addend 2 within the specified tolerance. For example,
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-- : addend_1 = 2 is almost equal to addend_2 = -1 with a
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-- : addend_1 = 2 is almost equal to addend_2 = -1 with a
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-- : tolerance of 3, but not a tolerance of 1. Actual function is
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-- : tolerance of 3, but not a tolerance of 1. Actual function is
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-- : AE = '1' when (A1 <= A2 + T) and (A1 >= A2 - T) else '0'
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-- : AE = '1' when (A1 <= A2 + T) and (A1 >= A2 - T) else '0'
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-- : This is an inherently signed function.
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-- : This is an inherently signed function.
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-- : Signed Overflow/Underflow is logically equivalent to
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-- : Signed Overflow/Underflow is logically equivalent to
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-- : S_Sum/Dif(16) xor S_Sum/Dif(15), since the apparent result
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-- : S_Sum/Dif(16) xor S_Sum/Dif(15), since the apparent result
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-- : changes sign while the internal sign bit does not. For example
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-- : changes sign while the internal sign bit doesn't. For example
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-- : |8000| will result in (-)8000 due to the way the internal
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-- : |8000| will result in (-)8000 due to the way the internal
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-- : logic handles sign extension. Thus, the O bit should be
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-- : logic handles sign extension. Thus, the O bit should be
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-- : checked when performing signed math
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-- : checked when performing signed math
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-- : Decimal Adjust converts the contents of a register into its BCD
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-- : Decimal Adjust converts the contents of a register into its BCD
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-- : equivalent. This can be used to get the base 10 representation
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-- : equivalent. This can be used to get the base 10 representation
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-- : of a value for conversion to ASCII. There are two variants,
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-- : of a value for conversion to ASCII. There are two variants,
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-- : Byte and Word. Note that conversion times are fairly long,
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-- : Byte and Word. Note that conversion times are fairly long,
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-- : since we are repeatedly issuing division commands, but it is
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-- : since we are repeatedly issuing division commands, but it is
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-- : still faster than software emulation.
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-- : still faster than software emulation.
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-- : The Byte conversion only operates on the lower 8 bits, and sets
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-- : The Byte conversion only operates on the lower 8 bits, and
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-- : the Z and N flags. The N flag is only set when SDAB is used
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-- : sets the Z and N flags. The N flag is only set when SDAB is
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-- : and the signed value of the register is negative. The O bit is
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-- : used and the signed value of the register is negative. The O
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-- : set if the upper byte of the register is non-zero, but does
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-- : bit is set if the upper byte of the register is non-zero, but
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-- : not actually result in an calculation error.
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-- : does not actually result in an calculation error.
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-- : Examples:
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-- : Examples:
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-- : UDAB 0x00FE -> 0x0254, Flags -> 0x0
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-- : UDAB 0x00FE -> 0x0254, Flags -> 0x0
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-- : SDAB 0x00FE -> 0x0002, Flags -> 0x4
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-- : SDAB 0x00FE -> 0x0002, Flags -> 0x4
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-- : The Word conversion uses the entire 16-bit word, and uses the
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-- : The Word conversion uses the entire 16-bit word, and uses the
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-- : Flags register to hold the Tens of Thousands place. Note that
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-- : Flags register to hold the Tens of Thousands place. Note that
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-- : the N flag is still used for signed conversions, while it may
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-- : the N flag is still used for signed conversions, while it may
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-- : be used as a data bit for unsigned conversions.
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-- : be used as a data bit for unsigned conversions.
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-- : Examples:
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-- : Examples:
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-- : UDAW 0xD431 -> 0x4321, Flags -> 0x5 ('0', MSB, MSB-1, MSB-2)
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-- : UDAW 0xD431 -> 0x4321, Flags -> 0x5 ('0', MSB, MSB-1, MSB-2)
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-- : SDAW 0xD431 -> 0x1216, Flags -> 0x5 ('0', N , MSB , MSB-1)
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-- : SDAW 0xD431 -> 0x1216, Flags -> 0x5 ('0', N , MSB , MSB-1)
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--
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-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x00 AAAAAAAA Register 0 ( 7:0) (RW)
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-- 0x00 AAAAAAAA Register 0 ( 7:0) (RW)
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-- 0x01 AAAAAAAA Register 0 (15:8) (RW)
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-- 0x01 AAAAAAAA Register 0 (15:8) (RW)
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-- 0x02 AAAAAAAA Register 1 ( 7:0) (RW)
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-- 0x02 AAAAAAAA Register 1 ( 7:0) (RW)
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-- 0x19 -------- Reserved (--)
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-- 0x19 -------- Reserved (--)
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-- 0x1A -------- Reserved (--)
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-- 0x1A -------- Reserved (--)
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-- 0x1B -------- Reserved (--)
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-- 0x1B -------- Reserved (--)
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-- 0x1C AAAAAAAA Tolerance ( 7:0) (RW)
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-- 0x1C AAAAAAAA Tolerance ( 7:0) (RW)
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-- 0x1D AAAAAAAA Tolerance (15:8) (RW)
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-- 0x1D AAAAAAAA Tolerance (15:8) (RW)
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-- 0x1E E---DCBA Status & Flags (RW)
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-- 0x1E BBBBBAAA Instruction Register (RW)
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-- A = Operand (register select)
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-- B = Opcode (instruction select)
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-- 0x1F E---DCBA Status & Flags (RW)
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-- A = Zero Flag
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-- A = Zero Flag
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-- B = Carry Flag
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-- B = Carry Flag
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-- C = Negative Flag
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-- C = Negative Flag
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-- D = Overflow / Error Flag
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-- D = Overflow / Error Flag
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-- E = Busy Flag (1 = busy, 0 = idle)
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-- E = Busy Flag (1 = busy, 0 = idle)
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-- 0x1F BBBBBAAA Instruction Register (RW)
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-- A = Operand (register select)
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-- B = Opcode (instruction select)
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--
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--
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-- Instruction Map:
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-- Instruction Map:
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-- OP_T0X "0000 0xxx" : Transfer R0 to Rx R0 -> Rx (Sets Z,N)
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-- OP_T0X "0000 0xxx" : Transfer R0 to Rx R0 -> Rx (Sets Z,N)
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-- OP_TX0 "0000 1xxx" : Transfer Rx to R0 Rx -> R0 (Sets Z,N)
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-- OP_TX0 "0000 1xxx" : Transfer Rx to R0 Rx -> R0 (Sets Z,N)
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-- OP_CLR "0001 0xxx" : Set Rx to 0 0x00 -> Rx (Sets Z,N)
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-- OP_CLR "0001 0xxx" : Set Rx to 0 0x00 -> Rx (Sets Z,N)
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| Line 145... |
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-- OP_BINV "1101 1xxx" : Bitwise logical NOT #Rx -> Rx
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-- OP_BINV "1101 1xxx" : Bitwise logical NOT #Rx -> Rx
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-- OP_BSFL "1110 0xxx" : Logical Shift Left Rx<<1,0 -> Rx
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-- OP_BSFL "1110 0xxx" : Logical Shift Left Rx<<1,0 -> Rx
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-- OP_BROL "1110 1xxx" : Logical Rotate Left Rx<<1,C -> Rx,C
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-- OP_BROL "1110 1xxx" : Logical Rotate Left Rx<<1,C -> Rx,C
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-- OP_BSFR "1111 0xxx" : Logical Shift Right 0,Rx>>1 -> Rx
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-- OP_BSFR "1111 0xxx" : Logical Shift Right 0,Rx>>1 -> Rx
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-- OP_BROR "1111 1xxx" : Logical Rotate Right C,Rx>>1 -> Rx,C
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-- OP_BROR "1111 1xxx" : Logical Rotate Right C,Rx>>1 -> Rx,C
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--
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-- Revision History
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-- Author Date Change
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------------------ -------- --------------------------------------------------
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-- Seth Henry 07/19/06 Design Start
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-- Seth Henry 03/13/15 Added "Almost Equal" instruction
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-- Seth Henry 12/19/19 Renamed to o8_alu16 to fit "theme"
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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Line 241... |
constant OP_BROL : std_logic_vector(4 downto 0) := "11101";
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constant OP_BROL : std_logic_vector(4 downto 0) := "11101";
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constant OP_BSFR : std_logic_vector(4 downto 0) := "11110";
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constant OP_BSFR : std_logic_vector(4 downto 0) := "11110";
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constant OP_BROR : std_logic_vector(4 downto 0) := "11111";
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constant OP_BROR : std_logic_vector(4 downto 0) := "11111";
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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constant User_Addr : std_logic_vector(15 downto 5):= Address(15 downto 5);
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constant User_Addr : std_logic_vector(15 downto 5):=
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Address(15 downto 5);
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alias Comp_Addr is Bus_Address(15 downto 5);
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alias Comp_Addr is Bus_Address(15 downto 5);
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signal Reg_Addr : std_logic_vector(4 downto 0);
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signal Reg_Addr : std_logic_vector(4 downto 0);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic;
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signal Wr_En : std_logic;
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signal Wr_En : std_logic;
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| Line 306... |
Line 314... |
signal s_prod : signed(33 downto 0);
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signal s_prod : signed(33 downto 0);
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signal IDIV_Start : std_logic;
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signal IDIV_Start : std_logic;
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signal IDIV_Busy : std_logic;
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signal IDIV_Busy : std_logic;
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constant N : integer := 16; -- Width of Operands
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constant DIV_WIDTH : integer := 16; -- Width of Operands
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signal q : std_logic_vector(N*2-1 downto 0);
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signal q : std_logic_vector(DIV_WIDTH*2-1 downto 0);
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signal diff : std_logic_vector(N downto 0);
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signal diff : std_logic_vector(DIV_WIDTH downto 0);
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signal count : integer range 0 to N + 1;
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signal count : integer range 0 to DIV_WIDTH + 1;
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signal Quotient_i : std_logic_vector(15 downto 0);
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signal Quotient_i : std_logic_vector(15 downto 0);
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signal Quotient : std_logic_vector(15 downto 0);
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signal Quotient : std_logic_vector(15 downto 0);
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signal Remainder_i : std_logic_vector(15 downto 0);
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signal Remainder_i : std_logic_vector(15 downto 0);
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Line 352... |
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-- Combinational logic for the Decimal Adjust logic
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-- Combinational logic for the Decimal Adjust logic
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DAA_result <= DAA_p4 & DAA_p3 & DAA_p2 & DAA_p1 & DAA_p0;
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DAA_result <= DAA_p4 & DAA_p3 & DAA_p2 & DAA_p1 & DAA_p0;
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-- Combinational logic for the division logic
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-- Combinational logic for the division logic
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diff <= ('0' & Q(N*2-2 downto N-1)) - ('0' & Divisor);
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diff <= ('0' & Q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
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Quotient_i <= q(N-1 downto 0);
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('0' & Divisor);
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Remainder_i <= q(N*2-1 downto N);
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Quotient_i <= q(DIV_WIDTH-1 downto 0);
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Remainder_i <= q(DIV_WIDTH*2-1 downto DIV_WIDTH);
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ALU_proc: process( Clock, Reset )
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ALU_proc: process( Clock, Reset )
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variable Reg_Sel : integer;
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variable Reg_Sel : integer;
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variable Oper_Sel : integer;
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variable Oper_Sel : integer;
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Wr_En <= '0';
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Wr_En <= '0';
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Wr_Data_q <= (others => '0');
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Wr_Data_q <= (others => '0');
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= (others => '0');
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Rd_Data <= OPEN8_NULLBUS;
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Reg_Addr <= (others => '0');
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Reg_Addr <= (others => '0');
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Opcode <= (others => '0');
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Opcode <= (others => '0');
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Operand_Sel <= (others => '0');
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Operand_Sel <= (others => '0');
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Tolerance <= (others => '0');
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Tolerance <= (others => '0');
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Start <= '0';
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Start <= '0';
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| Line 387... |
Line 396... |
DAA_p4 <= (others => '0');
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DAA_p4 <= (others => '0');
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DAA_p3 <= (others => '0');
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DAA_p3 <= (others => '0');
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DAA_p2 <= (others => '0');
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DAA_p2 <= (others => '0');
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IDIV_Start <= '0';
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IDIV_Start <= '0';
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q <= (others => '0');
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q <= (others => '0');
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count <= N;
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count <= DIV_WIDTH;
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IDIV_Busy <= '0';
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IDIV_Busy <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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-- For convenience, convert these to integers and assign them to
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-- For convenience, convert these to integers and assign them to
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-- variables
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-- variables
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Reg_Sel := conv_integer(Reg_Addr(3 downto 1));
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Reg_Sel := conv_integer(Reg_Addr(3 downto 1));
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| Line 418... |
Line 427... |
Tolerance(7 downto 0) <= Wr_Data_q;
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Tolerance(7 downto 0) <= Wr_Data_q;
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when "11101" => -- 0x1D -> Tolerance.u
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when "11101" => -- 0x1D -> Tolerance.u
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Tolerance(15 downto 8) <= Wr_Data_q;
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Tolerance(15 downto 8) <= Wr_Data_q;
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when "11110" => -- 0x1E -> Status register
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when "11110" => -- 0x1E -> Opcode register
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null;
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when "11111" => -- 0x1F -> Control register
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Start <= '1';
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Opcode <= Wr_Data_q(7 downto 3);
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Opcode <= Wr_Data_q(7 downto 3);
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Operand_Sel <= Wr_Data_q(2 downto 0);
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Operand_Sel <= Wr_Data_q(2 downto 0);
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when "11111" => -- 0x1F -> Status/Start register
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Start <= '1';
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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Rd_Data <= (others => '0');
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En <= Addr_Match and Rd_Enable;
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Rd_En <= Addr_Match and Rd_Enable;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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case( Reg_Addr )is
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case( Reg_Addr )is
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when "00000" | "00010" | "00100" | "00110" |
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when "00000" | "00010" | "00100" | "00110" |
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| Line 445... |
Line 453... |
Rd_Data <= regfile(Reg_Sel)(15 downto 8);
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Rd_Data <= regfile(Reg_Sel)(15 downto 8);
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when "11100" => -- 0x1C -> Tolerance.l
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when "11100" => -- 0x1C -> Tolerance.l
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Rd_Data <= Tolerance(7 downto 0);
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Rd_Data <= Tolerance(7 downto 0);
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when "11101" => -- 0x1D -> Tolerance.u
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when "11101" => -- 0x1D -> Tolerance.u
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Rd_Data <= Tolerance(15 downto 8);
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Rd_Data <= Tolerance(15 downto 8);
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when "11110" => -- 0x1E -> Flags & Status register
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when "11110" => -- 0x1E -> Opcode register
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Rd_Data <= Busy & "000" & Flags;
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when "11111" => -- 0x1F -> Control register
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Rd_Data <= Opcode & Operand_Sel;
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Rd_Data <= Opcode & Operand_Sel;
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when "11111" => -- 0x1F -> Flags & Status register
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Rd_Data <= Busy & "000" & Flags;
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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Busy <= '1';
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Busy <= '1';
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| Line 462... |
Line 471... |
Busy <= '0';
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Busy <= '0';
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if( Start = '1' )then
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if( Start = '1' )then
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alu_ctrl <= LOAD;
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alu_ctrl <= LOAD;
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end if;
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end if;
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-- Load the operands from the register file. We also check for specific
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-- Load the operands from the reg file. We also check for specific
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-- opcodes to set the DAA mode (signed vs unsigned). This is the only
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-- opcodes to set the DAA mode (signed vs unsigned). This is the only
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-- place where we READ the register file outside of the bus interface
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-- place where we READ the register file outside of the bus interface
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when LOAD =>
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when LOAD =>
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Operand_1 <= regfile(0);
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Operand_1 <= regfile(0);
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Operand_2 <= regfile(Oper_Sel);
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Operand_2 <= regfile(Oper_Sel);
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| Line 513... |
Line 522... |
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when OP_SADD =>
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when OP_SADD =>
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s_accum <= S_Addend_1 + S_Addend_2;
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s_accum <= S_Addend_1 + S_Addend_2;
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when OP_UADD =>
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when OP_UADD =>
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u_accum <= ('0' & Operand_1) + ('0' & Operand_2);
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u_accum <= ('0' & Operand_1) +
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('0' & Operand_2);
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|
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when OP_UADC =>
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when OP_UADC =>
|
u_accum <= ('0' & Operand_1) + ('0' & Operand_2) + Flags(FLAG_C);
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u_accum <= ('0' & Operand_1) +
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('0' & Operand_2) +
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Flags(FLAG_C);
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when OP_SSUB | OP_SCMP =>
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when OP_SSUB | OP_SCMP =>
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s_accum <= S_Addend_1 - S_Addend_2;
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s_accum <= S_Addend_1 - S_Addend_2;
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|
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when OP_USUB | OP_UCMP =>
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when OP_USUB | OP_UCMP =>
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u_accum <= ('0' & U_Addend_1) - ('0' & U_Addend_2);
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u_accum <= ('0' & U_Addend_1) -
|
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('0' & U_Addend_2);
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|
|
when OP_USBC =>
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when OP_USBC =>
|
u_accum <= ('0' & U_Addend_1) - ('0' & U_Addend_2) - Flags(FLAG_C);
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u_accum <= ('0' & U_Addend_1) -
|
|
('0' & U_Addend_2) -
|
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Flags(FLAG_C);
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|
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when OP_ACMP =>
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when OP_ACMP =>
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-- Perform the function
|
-- Perform the function
|
-- AE = '1' when (A1 <= A2 + T) and (A1 >= A2 - T) else '0'
|
-- AE = '1' when (A1 <= A2 + T) and (A1 >= A2 - T) else '0'
|
Almost_Equal <= '0';
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Almost_Equal <= '0';
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| Line 775... |
Line 790... |
|
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IDIV_Busy <= '0';
|
IDIV_Busy <= '0';
|
if( IDIV_Start = '1' )then
|
if( IDIV_Start = '1' )then
|
IDIV_Busy <= '1';
|
IDIV_Busy <= '1';
|
count <= 0;
|
count <= 0;
|
q <= conv_std_logic_vector(0,N) & Dividend;
|
q <= conv_std_logic_vector(0,DIV_WIDTH) & Dividend;
|
elsif( count < N )then
|
elsif( count < DIV_WIDTH )then
|
IDIV_Busy <= '1';
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IDIV_Busy <= '1';
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count <= count + 1;
|
count <= count + 1;
|
q <= diff(N-1 downto 0) & q(N-2 downto 0) & '1';
|
q <= diff(DIV_WIDTH-1 downto 0) &
|
if( diff(N) = '1' )then
|
q(DIV_WIDTH-2 downto 0) &
|
q <= q(N*2-2 downto 0) & '0';
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'1';
|
|
if( diff(DIV_WIDTH) = '1' )then
|
|
q <= q(DIV_WIDTH*2-2 downto 0) & '0';
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end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- Fire on the falling edge of Busy
|
-- Fire on the falling edge of Busy
|
Busy_q <= Busy;
|
Busy_q <= Busy;
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