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-------------------------------------------------------------------
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-------------------------------------------------------------------
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constant User_Addr : std_logic_vector(15 downto 5):=
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constant User_Addr : std_logic_vector(15 downto 5):=
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Address(15 downto 5);
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Address(15 downto 5);
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alias Comp_Addr is Bus_Address(15 downto 5);
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alias Comp_Addr is Bus_Address(15 downto 5);
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signal Reg_Addr : std_logic_vector(4 downto 0) := (others => '0');
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signal Reg_Addr : std_logic_vector(4 downto 0) :=
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(others => '0');
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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signal Wr_En : std_logic := '0';
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signal Wr_En : std_logic := '0';
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signal Wr_Data_q : DATA_TYPE := (others => '0');
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signal Wr_Data_q : DATA_TYPE := (others => '0');
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signal Rd_En : std_logic := '0';
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signal Rd_En : std_logic := '0';
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signal regfile : REG_ARRAY := (
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signal regfile : REG_ARRAY := (
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x"0000",x"0000",x"0000",x"0000",
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x"0000",x"0000",x"0000",x"0000",
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x"0000",x"0000",x"0000",x"0000");
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x"0000",x"0000",x"0000",x"0000");
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signal Start : std_logic := '0';
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signal Start : std_logic := '0';
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signal Opcode : std_logic_vector(4 downto 0) := (others => '0');
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signal Opcode : std_logic_vector(4 downto 0) :=
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signal Operand_Sel : std_logic_vector(2 downto 0) := (others => '0');
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(others => '0');
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signal Operand_Sel : std_logic_vector(2 downto 0) :=
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(others => '0');
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signal Tolerance : std_logic_vector(15 downto 0) :=
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(others => '0');
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signal Tolerance : std_logic_vector(15 downto 0) := (others => '0');
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signal High_Tol : signed(16 downto 0) := (others => '0');
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signal High_Tol : signed(16 downto 0) := (others => '0');
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signal Low_Tol : signed(16 downto 0) := (others => '0');
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signal Low_Tol : signed(16 downto 0) := (others => '0');
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signal Almost_Equal : std_logic := '0';
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signal Almost_Equal : std_logic := '0';
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constant FLAG_Z : integer := 0;
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constant FLAG_Z : integer := 0;
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constant FLAG_C : integer := 1;
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constant FLAG_C : integer := 1;
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constant FLAG_N : integer := 2;
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constant FLAG_N : integer := 2;
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constant FLAG_O : integer := 3;
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constant FLAG_O : integer := 3;
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signal Flags : std_logic_vector(3 downto 0) := (others => '0');
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signal Flags : std_logic_vector(3 downto 0) :=
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(others => '0');
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type ALU_STATES is ( IDLE, LOAD, EXECUTE, IDIV_INIT, IDIV_WAIT,
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type ALU_STATES is ( IDLE, LOAD, EXECUTE, IDIV_INIT, IDIV_WAIT,
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DAW_INIT, DAB_INIT, DAA_WAIT1, DAA_STEP2,
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DAW_INIT, DAB_INIT, DAA_WAIT1, DAA_STEP2,
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DAA_WAIT2, DAA_STEP3, DAA_WAIT3, DAA_STEP4,
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DAA_WAIT2, DAA_STEP3, DAA_WAIT3, DAA_STEP4,
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STORE );
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STORE );
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signal alu_ctrl : ALU_STATES := IDLE;
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signal alu_ctrl : ALU_STATES := IDLE;
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signal Busy : std_logic := '0';
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signal Busy : std_logic := '0';
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signal Busy_q : std_logic := '0';
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signal Busy_q : std_logic := '0';
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signal Operand_1 : std_logic_vector(15 downto 0) := (others => '0');
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signal Operand_1 : std_logic_vector(15 downto 0) :=
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signal Operand_2 : std_logic_vector(15 downto 0) := (others => '0');
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(others => '0');
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signal Operand_2 : std_logic_vector(15 downto 0) :=
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(others => '0');
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alias Dividend is Operand_1;
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alias Dividend is Operand_1;
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alias Divisor is Operand_2;
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alias Divisor is Operand_2;
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alias u_Operand_1 is Operand_1;
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alias u_Operand_1 is Operand_1;
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Line 311... |
signal s_Operand_2 : signed(16 downto 0) := (others => '0');
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signal s_Operand_2 : signed(16 downto 0) := (others => '0');
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alias s_Addend_1 is S_Operand_1;
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alias s_Addend_1 is S_Operand_1;
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alias s_Addend_2 is S_Operand_2;
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alias s_Addend_2 is S_Operand_2;
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signal u_accum : std_logic_vector(16 downto 0) := (others => '0');
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signal u_accum : std_logic_vector(16 downto 0) :=
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(others => '0');
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alias u_data is u_accum(15 downto 0);
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alias u_data is u_accum(15 downto 0);
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alias u_sign is u_accum(15);
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alias u_sign is u_accum(15);
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alias u_carry is u_accum(16);
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alias u_carry is u_accum(16);
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signal u_prod : std_logic_vector(31 downto 0) := (others => '0');
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signal u_prod : std_logic_vector(31 downto 0) :=
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(others => '0');
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signal s_accum : signed(16 downto 0) := (others => '0');
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signal s_accum : signed(16 downto 0) := (others => '0');
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alias s_data is s_accum(15 downto 0);
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alias s_data is s_accum(15 downto 0);
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alias s_sign is s_accum(15);
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alias s_sign is s_accum(15);
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alias s_ovf is s_accum(16);
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alias s_ovf is s_accum(16);
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Line 340... |
signal diff : std_logic_vector(DIV_WIDTH downto 0) :=
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signal diff : std_logic_vector(DIV_WIDTH downto 0) :=
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(others => '0');
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(others => '0');
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signal count : integer range 0 to DIV_WIDTH + 1 := 0;
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signal count : integer range 0 to DIV_WIDTH + 1 := 0;
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signal Quotient_i : std_logic_vector(15 downto 0) := (others => '0');
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signal Quotient_i : std_logic_vector(15 downto 0) :=
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signal Quotient : std_logic_vector(15 downto 0) := (others => '0');
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(others => '0');
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signal Quotient : std_logic_vector(15 downto 0) :=
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(others => '0');
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signal Remainder_i : std_logic_vector(15 downto 0) :=
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(others => '0');
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signal Remainder_i : std_logic_vector(15 downto 0) := (others => '0');
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signal Remainder : std_logic_vector(15 downto 0) :=
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signal Remainder : std_logic_vector(15 downto 0) := (others => '0');
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(others => '0');
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signal DAA_intreg : std_logic_vector(15 downto 0) :=
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(others => '0');
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signal DAA_intreg : std_logic_vector(15 downto 0) := (others => '0');
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signal DAA_mode : std_logic := '0';
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signal DAA_mode : std_logic := '0';
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signal DAA_sign : std_logic := '0';
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signal DAA_sign : std_logic := '0';
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signal DAA_p4 : std_logic_vector(3 downto 0) := (others => '0');
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signal DAA_p4 : std_logic_vector(3 downto 0) :=
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signal DAA_p3 : std_logic_vector(3 downto 0) := (others => '0');
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(others => '0');
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signal DAA_p2 : std_logic_vector(3 downto 0) := (others => '0');
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signal DAA_p3 : std_logic_vector(3 downto 0) :=
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(others => '0');
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signal DAA_p2 : std_logic_vector(3 downto 0) :=
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(others => '0');
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alias DAA_p1 is Quotient(3 downto 0);
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alias DAA_p1 is Quotient(3 downto 0);
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alias DAA_p0 is Remainder(3 downto 0);
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alias DAA_p0 is Remainder(3 downto 0);
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signal DAA_result : std_logic_vector(19 downto 0) := (others => '0');
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signal DAA_result : std_logic_vector(19 downto 0) :=
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(others => '0');
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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