| Line 153... |
Line 153... |
------------------ -------- --------------------------------------------------
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------------------ -------- --------------------------------------------------
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-- Seth Henry 07/19/06 Design Start
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-- Seth Henry 07/19/06 Design Start
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-- Seth Henry 03/13/15 Added "Almost Equal" instruction
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-- Seth Henry 03/13/15 Added "Almost Equal" instruction
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-- Seth Henry 12/19/19 Renamed to o8_alu16 to fit "theme"
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-- Seth Henry 12/19/19 Renamed to o8_alu16 to fit "theme"
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-- Seth Henry 04/10/20 Comment and code cleanup
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-- Seth Henry 04/10/20 Comment and code cleanup
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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| Line 165... |
Line 166... |
library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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|
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entity o8_alu16 is
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entity o8_alu16 is
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generic(
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generic(
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Reset_Level : std_logic;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Clock : in std_logic;
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Reset : in std_logic;
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--
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic
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Interrupt : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_alu16 is
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architecture behave of o8_alu16 is
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- Opcode Definitions (should match the table above)
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-- Opcode Definitions (should match the table above)
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-- Register Manipulation
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-- Register Manipulation
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constant OP_T0X : std_logic_vector(4 downto 0) := "00000";
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constant OP_T0X : std_logic_vector(4 downto 0) := "00000";
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constant OP_TX0 : std_logic_vector(4 downto 0) := "00001";
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constant OP_TX0 : std_logic_vector(4 downto 0) := "00001";
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