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--
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--
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-- VHDL Units : o8_async_serial
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-- VHDL Units : o8_async_serial
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-- Description: Provides a single 8-bit, asynchronous transceiver. While the
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-- Description: Provides a single 8-bit, asynchronous transceiver. While the
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-- width is fixed at 8-bits, the bit rate and parity controls
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-- width is fixed at 8-bits, the bit rate and parity controls
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-- are settable via generics.
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-- are settable via generics.
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--
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-- Note: The baud rate generator will produce an approximate frequency. The
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-- final bit rate should be within +/- 1% of the true bit rate to
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-- ensure the receiver can successfully receive. With a sufficiently
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-- high core clock, this is generally achievable for common PC serial
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-- data rates.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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signal CTS_sr : std_logic_vector(3 downto 0) := "0000";
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signal CTS_sr : std_logic_vector(3 downto 0) := "0000";
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alias CTS_Okay is CTS_sr(3);
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alias CTS_Okay is CTS_sr(3);
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signal RX_FIFO_Wr_En : std_logic := '0';
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signal RX_FIFO_Wr_En : std_logic := '0';
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signal RX_FIFO_Wr_Data : DATA_TYPE;
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signal RX_FIFO_Wr_Data : DATA_TYPE := x"00";
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signal RX_FIFO_Rd_En : std_logic;
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signal RX_FIFO_Rd_En : std_logic := '0';
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signal RX_FIFO_Empty : std_logic;
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signal RX_FIFO_Empty : std_logic := '0';
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signal RX_FIFO_AFull : std_logic;
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signal RX_FIFO_AFull : std_logic := '0';
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signal RX_FIFO_Rd_Data : DATA_TYPE;
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signal RX_FIFO_Rd_Data : DATA_TYPE := x"00";
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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