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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : o8_async_serial
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-- VHDL Units : o8_async_serial
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-- Description: Provides a single 8-bit, asynchronous transceiver. While the
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-- Description: Provides a single 8-bit, asynchronous transceiver. While the
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-- width is fixed at 8-bits, the bit rate and parity controls
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-- width is fixed at 8-bits, the bit rate and parity controls
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-- are settable via generics.
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-- are settable via generics.
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--
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--
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- 0x00 AAAAAAAA TX Data (WR) RX Data (RD) (RW)
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-- 0x01 DCBA---- FIFO Status (RO)
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-- A: RX FIFO Empty
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-- B: RX FIFO almost full (922/1024)
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-- C: TX FIFO Empty
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-- D: TX FIFO almost full (922/1024)
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--
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-- Note: The baud rate generator will produce an approximate frequency. The
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-- Note: The baud rate generator will produce an approximate frequency. The
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-- final bit rate should be within +/- 1% of the true bit rate to
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-- final bit rate should be within +/- 1% of the true bit rate to
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-- ensure the receiver can successfully receive. With a sufficiently
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-- ensure the receiver can successfully receive. With a sufficiently
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-- high core clock, this is generally achievable for common PC serial
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-- high core clock, this is generally achievable for common PC serial
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-- data rates.
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-- data rates.
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--
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-- Revision History
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 12/20/19 Design Start
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-- Seth Henry 04/10/20 Code cleanup and register documentation
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 41... |
Line 56... |
library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_async_serial is
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entity o8_async_serial is
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generic(
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generic(
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Disable_Transmit : boolean := FALSE;
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Disable_Receive : boolean := FALSE;
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Bit_Rate : real;
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Bit_Rate : real;
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Enable_Parity : boolean;
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Enable_Parity : boolean;
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Parity_Odd_Even_n : std_logic;
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Parity_Odd_Even_n : std_logic;
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Sys_Freq : real;
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Sys_Freq : real;
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Reset_Level : std_logic;
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Reset_Level : std_logic;
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| Line 132... |
Line 149... |
end if;
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end if;
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RTS_Out <= not RX_FIFO_AFull;
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RTS_Out <= not RX_FIFO_AFull;
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end if;
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end if;
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end process;
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end process;
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TX_Disabled : if( Disable_Transmit )generate
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TX_FIFO_Empty <= '1';
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TX_FIFO_AFull <= '0';
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TX_Out <= '1';
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end generate;
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TX_Enabled : if( not Disable_Transmit )generate
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TX_FIFO_Wr_En <= Wr_Enable and Addr_Match and not Reg_Addr;
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TX_FIFO_Wr_En <= Wr_Enable and Addr_Match and not Reg_Addr;
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FIFO_Reset <= '1' when Reset = Reset_Level else '0';
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FIFO_Reset <= '1' when Reset = Reset_Level else '0';
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U_TX_FIFO : entity work.fifo_1k_core
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U_TX_FIFO : entity work.fifo_1k_core
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| Line 205... |
Line 232... |
--
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--
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Tx_Out => TX_Out,
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Tx_Out => TX_Out,
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Tx_Done => Tx_Done
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Tx_Done => Tx_Done
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);
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);
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end generate;
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RX_Disabled : if( Disable_Transmit )generate
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RX_FIFO_Empty <= '1';
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RX_FIFO_AFull <= '0';
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RX_FIFO_Rd_Data <= x"00";
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end generate;
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RX_Enabled : if( not Disable_Receive )generate
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U_RX : entity work.async_ser_rx
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U_RX : entity work.async_ser_rx
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generic map(
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generic map(
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Reset_Level => Reset_Level,
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Reset_Level => Reset_Level,
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Enable_Parity => Enable_Parity,
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Enable_Parity => Enable_Parity,
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Parity_Odd_Even_n => Parity_Odd_Even_n,
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Parity_Odd_Even_n => Parity_Odd_Even_n,
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| Line 237... |
Line 276... |
empty => RX_FIFO_Empty,
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empty => RX_FIFO_Empty,
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almost_full => RX_FIFO_AFull,
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almost_full => RX_FIFO_AFull,
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q => RX_FIFO_Rd_Data
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q => RX_FIFO_Rd_Data
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);
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);
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end generate;
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end architecture;
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end architecture;
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No newline at end of file
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No newline at end of file
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