| Line 69... |
Line 69... |
);
|
);
|
port(
|
port(
|
Clock : in std_logic;
|
Clock : in std_logic;
|
Reset : in std_logic;
|
Reset : in std_logic;
|
--
|
--
|
Bus_Address : in ADDRESS_TYPE;
|
Open8_Bus : in OPEN8_BUS_TYPE;
|
Wr_Enable : in std_logic;
|
|
Wr_Data : in DATA_TYPE;
|
|
Rd_Enable : in std_logic;
|
|
Rd_Data : out DATA_TYPE;
|
Rd_Data : out DATA_TYPE;
|
--
|
--
|
TX_Out : out std_logic;
|
TX_Out : out std_logic;
|
CTS_In : in std_logic;
|
CTS_In : in std_logic;
|
RX_In : in std_logic;
|
RX_In : in std_logic;
|
| Line 88... |
Line 85... |
|
|
signal FIFO_Reset : std_logic := '0';
|
signal FIFO_Reset : std_logic := '0';
|
|
|
constant User_Addr : std_logic_vector(15 downto 1) :=
|
constant User_Addr : std_logic_vector(15 downto 1) :=
|
Address(15 downto 1);
|
Address(15 downto 1);
|
alias Comp_Addr is Bus_Address(15 downto 1);
|
alias Comp_Addr is Open8_Bus.Address(15 downto 1);
|
signal Addr_Match : std_logic := '0';
|
signal Addr_Match : std_logic := '0';
|
|
|
alias Reg_Addr is Bus_Address(0);
|
alias Reg_Addr is Open8_Bus.Address(0);
|
signal Reg_Sel : std_logic := '0';
|
signal Reg_Sel : std_logic := '0';
|
signal Rd_En : std_logic := '0';
|
signal Rd_En : std_logic := '0';
|
|
|
signal TX_FIFO_Wr_En : std_logic := '0';
|
signal TX_FIFO_Wr_En : std_logic := '0';
|
alias TX_FIFO_Wr_Data is Wr_Data;
|
alias TX_FIFO_Wr_Data is Open8_Bus.Wr_Data;
|
signal TX_FIFO_Rd_En : std_logic := '0';
|
signal TX_FIFO_Rd_En : std_logic := '0';
|
signal TX_FIFO_Empty : std_logic := '0';
|
signal TX_FIFO_Empty : std_logic := '0';
|
signal TX_FIFO_AFull : std_logic := '0';
|
signal TX_FIFO_AFull : std_logic := '0';
|
signal TX_FIFO_Rd_Data : DATA_TYPE := x"00";
|
signal TX_FIFO_Rd_Data : DATA_TYPE := x"00";
|
|
|
| Line 134... |
Line 131... |
Rd_En <= '0';
|
Rd_En <= '0';
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
RTS_Out <= '0';
|
RTS_Out <= '0';
|
elsif( rising_edge( Clock ) )then
|
elsif( rising_edge( Clock ) )then
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_En <= Rd_Enable and Addr_Match;
|
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
|
Reg_Sel <= Reg_Addr;
|
Reg_Sel <= Reg_Addr;
|
if( Rd_En = '1' and Reg_Sel = '1' )then
|
if( Rd_En = '1' and Reg_Sel = '1' )then
|
Rd_Data(4) <= RX_FIFO_Empty;
|
Rd_Data(4) <= RX_FIFO_Empty;
|
Rd_Data(5) <= RX_FIFO_AFull;
|
Rd_Data(5) <= RX_FIFO_AFull;
|
Rd_Data(6) <= TX_FIFO_Empty;
|
Rd_Data(6) <= TX_FIFO_Empty;
|
| Line 159... |
Line 156... |
|
|
end generate;
|
end generate;
|
|
|
TX_Enabled : if( not Disable_Transmit )generate
|
TX_Enabled : if( not Disable_Transmit )generate
|
|
|
TX_FIFO_Wr_En <= Wr_Enable and Addr_Match and not Reg_Addr;
|
TX_FIFO_Wr_En <= Open8_Bus.Wr_En and
|
|
Addr_Match and
|
|
(not Reg_Addr);
|
|
|
FIFO_Reset <= '1' when Reset = Reset_Level else '0';
|
FIFO_Reset <= '1' when Reset = Reset_Level else '0';
|
|
|
U_TX_FIFO : entity work.fifo_1k_core
|
U_TX_FIFO : entity work.fifo_1k_core
|
port map(
|
port map(
|
| Line 262... |
Line 261... |
Rx_Data => RX_FIFO_Wr_Data,
|
Rx_Data => RX_FIFO_Wr_Data,
|
Rx_Valid => RX_FIFO_Wr_En,
|
Rx_Valid => RX_FIFO_Wr_En,
|
Rx_PErr => open
|
Rx_PErr => open
|
);
|
);
|
|
|
RX_FIFO_Rd_En <= Rd_Enable and Addr_Match and not Reg_Addr;
|
RX_FIFO_Rd_En <= Open8_Bus.Rd_En and
|
|
Addr_Match and
|
|
(not Reg_Addr);
|
|
|
U_RX_FIFO : entity work.fifo_1k_core
|
U_RX_FIFO : entity work.fifo_1k_core
|
port map(
|
port map(
|
aclr => FIFO_Reset,
|
aclr => FIFO_Reset,
|
clock => Clock,
|
clock => Clock,
|
