| Line 44... |
Line 44... |
-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 12/20/19 Design Start
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-- Seth Henry 12/20/19 Design Start
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-- Seth Henry 04/10/20 Code cleanup and register documentation
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-- Seth Henry 04/10/20 Code cleanup and register documentation
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 61... |
Line 62... |
Disable_Transmit : boolean := FALSE;
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Disable_Transmit : boolean := FALSE;
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Disable_Receive : boolean := FALSE;
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Disable_Receive : boolean := FALSE;
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Bit_Rate : real;
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Bit_Rate : real;
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Enable_Parity : boolean;
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Enable_Parity : boolean;
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Parity_Odd_Even_n : std_logic;
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Parity_Odd_Even_n : std_logic;
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Sys_Freq : real;
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Clock_Frequency : real;
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Reset_Level : std_logic;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Clock : in std_logic;
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Reset : in std_logic;
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--
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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--
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--
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TX_Out : out std_logic;
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TX_Out : out std_logic;
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CTS_In : in std_logic;
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CTS_In : in std_logic;
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| Line 81... |
Line 78... |
);
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);
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end entity;
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end entity;
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architecture behave of o8_async_serial is
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architecture behave of o8_async_serial is
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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signal FIFO_Reset : std_logic := '0';
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signal FIFO_Reset : std_logic := '0';
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constant User_Addr : std_logic_vector(15 downto 1) :=
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constant User_Addr : std_logic_vector(15 downto 1) :=
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Address(15 downto 1);
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Address(15 downto 1);
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alias Comp_Addr is Open8_Bus.Address(15 downto 1);
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alias Comp_Addr is Open8_Bus.Address(15 downto 1);
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| Line 107... |
Line 108... |
signal TX_Ctrl : TX_CTRL_STATES := IDLE;
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signal TX_Ctrl : TX_CTRL_STATES := IDLE;
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signal TX_Xmit : std_logic := '0';
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signal TX_Xmit : std_logic := '0';
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signal TX_Done : std_logic := '0';
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signal TX_Done : std_logic := '0';
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constant BAUD_RATE_DIV : integer := integer(Sys_Freq / Bit_Rate);
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constant BAUD_RATE_DIV : integer := integer(Clock_Frequency / Bit_Rate);
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signal CTS_sr : std_logic_vector(3 downto 0) := "0000";
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signal CTS_sr : std_logic_vector(3 downto 0) := "0000";
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alias CTS_Okay is CTS_sr(3);
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alias CTS_Okay is CTS_sr(3);
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signal RX_FIFO_Wr_En : std_logic := '0';
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signal RX_FIFO_Wr_En : std_logic := '0';
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