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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_async_serial.vhd] - Diff between revs 224 and 244

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Rev 224 Rev 244
Line 27... Line 27... 
--               are settable via generics.
 
--               are settable via generics.
 
--
 
--
 
-- Register Map:
 
-- Register Map:
 
-- Offset  Bitfield Description                        Read/Write
 
-- Offset  Bitfield Description                        Read/Write
 
--   0x00  AAAAAAAA TX Data (WR) RX Data (RD)             (RW)
 
--   0x00  AAAAAAAA TX Data (WR) RX Data (RD)             (RW)
 
--   0x01  DCBA---- FIFO Status                           (RO)
 
--   0x01  EDCBA--- FIFO Status                           (RO*)
 
--                  A: RX FIFO Empty
 
--                  A: RX Parity Error (write to clear)
 
--                  B: RX FIFO almost full (922/1024)
 
--                  B: RX FIFO Empty
 
--                  C: TX FIFO Empty
 
--                  C: RX FIFO almost full (922/1024)
 
--                  D: TX FIFO almost full (922/1024)
 
--                  D: TX FIFO Empty
 
 
 
--                  E: TX FIFO almost full (922/1024)
 
--
 
--
 
-- Note: The baud rate generator will produce an approximate frequency. The
 
-- Note: The baud rate generator will produce an approximate frequency. The
 
--        final bit rate should be within +/- 1% of the true bit rate to
 
--        final bit rate should be within +/- 1% of the true bit rate to
 
--        ensure the receiver can successfully receive. With a sufficiently
 
--        ensure the receiver can successfully receive. With a sufficiently
 
--        high core clock, this is generally achievable for common PC serial
 
--        high core clock, this is generally achievable for common PC serial
Line 45... Line 46... 
-- Author          Date     Change
 
-- Author          Date     Change
 
------------------ -------- ---------------------------------------------------
 
------------------ -------- ---------------------------------------------------
 
-- Seth Henry      12/20/19 Design Start
 
-- Seth Henry      12/20/19 Design Start
 
-- Seth Henry      04/10/20 Code cleanup and register documentation
 
-- Seth Henry      04/10/20 Code cleanup and register documentation
 
-- Seth Henry      04/16/20 Modified to use Open8 bus record
 
-- Seth Henry      04/16/20 Modified to use Open8 bus record
 
 
 
-- Seth Henry      05/18/20 Added write qualification input
 
 
 
 
 
library ieee;
 
library ieee;
 
use ieee.std_logic_1164.all;
 
use ieee.std_logic_1164.all;
 
use ieee.std_logic_unsigned.all;
 
use ieee.std_logic_unsigned.all;
 
use ieee.std_logic_arith.all;
 
use ieee.std_logic_arith.all;
Line 67... Line 69... 
  Clock_Frequency            : real;
 
  Clock_Frequency            : real;
 
  Address                    : ADDRESS_TYPE
 
  Address                    : ADDRESS_TYPE
 
);
 
);
 
port(
 
port(
 
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
 
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
 
 
 
  Write_Qual                 : in  std_logic := '1';
 
  Rd_Data                    : out DATA_TYPE;
 
  Rd_Data                    : out DATA_TYPE;
 
  --
 
  --
 
  TX_Out                     : out std_logic;
 
  TX_Out                     : out std_logic;
 
  CTS_In                     : in  std_logic;
 
  CTS_In                     : in  std_logic := '1';
 
  RX_In                      : in  std_logic;
 
  RX_In                      : in  std_logic := '1';
 
  RTS_Out                    : out std_logic
 
  RTS_Out                    : out std_logic
 
);
 
);
 
end entity;
 
end entity;
 
 
 
 
 
architecture behave of o8_async_serial is
 
architecture behave of o8_async_serial is
 
 
 
 
 
  alias Clock                is Open8_Bus.Clock;
 
  alias Clock                is Open8_Bus.Clock;
 
  alias Reset                is Open8_Bus.Reset;
 
  alias Reset                is Open8_Bus.Reset;
 
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
 
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
 
 
 
  alias Wr_En                is Open8_Bus.Wr_En;
 
 
 
  alias Wr_Data              is Open8_Bus.Wr_Data;
 
 
 
  alias Rd_En                is Open8_Bus.Rd_En;
 
 
 
 
 
  signal FIFO_Reset          : std_logic := '0';
 
  signal FIFO_Reset          : std_logic := '0';
 
 
 
 
 
  constant User_Addr         : std_logic_vector(15 downto 1) :=
 
  constant User_Addr         : std_logic_vector(15 downto 1) :=
 
                                Address(15 downto 1);
 
                                Address(15 downto 1);
 
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 1);
 
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 1);
 
  signal Addr_Match          : std_logic := '0';
 
  signal Addr_Match          : std_logic := '0';
 
 
 
 
 
  alias  Reg_Addr            is Open8_Bus.Address(0);
 
  alias  Reg_Sel_d           is Open8_Bus.Address(0);
 
  signal Reg_Sel             : std_logic := '0';
 
  signal Reg_Sel_q           : std_logic := '0';
 
  signal Rd_En               : std_logic := '0';
 
  signal Wr_En_d             : std_logic := '0';
 
 
 
  signal Wr_En_q             : std_logic := '0';
 
 
 
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
 
 
 
  signal Wr_Data_q           : DATA_TYPE := x"00";
 
 
 
  signal Rd_En_d             : std_logic := '0';
 
 
 
  signal Rd_En_q             : std_logic := '0';
 
 
 
 
 
  signal TX_FIFO_Wr_En       : std_logic := '0';
 
  signal TX_FIFO_Wr_En       : std_logic := '0';
 
  alias  TX_FIFO_Wr_Data     is Open8_Bus.Wr_Data;
 
  signal TX_FIFO_Wr_Data     : DATA_TYPE := x"00";
 
  signal TX_FIFO_Rd_En       : std_logic := '0';
 
  signal TX_FIFO_Rd_En       : std_logic := '0';
 
  signal TX_FIFO_Empty       : std_logic := '0';
 
  signal TX_FIFO_Empty       : std_logic := '0';
 
  signal TX_FIFO_AFull       : std_logic := '0';
 
  signal TX_FIFO_AFull       : std_logic := '0';
 
  signal TX_FIFO_Rd_Data     : DATA_TYPE := x"00";
 
  signal TX_FIFO_Rd_Data     : DATA_TYPE := x"00";
 
 
 
 
Line 120... Line 131... 
  signal RX_FIFO_Rd_En       : std_logic := '0';
 
  signal RX_FIFO_Rd_En       : std_logic := '0';
 
  signal RX_FIFO_Empty       : std_logic := '0';
 
  signal RX_FIFO_Empty       : std_logic := '0';
 
  signal RX_FIFO_AFull       : std_logic := '0';
 
  signal RX_FIFO_AFull       : std_logic := '0';
 
  signal RX_FIFO_Rd_Data     : DATA_TYPE := x"00";
 
  signal RX_FIFO_Rd_Data     : DATA_TYPE := x"00";
 
 
 
 
 
 
 
  signal Rx_PErr             : std_logic := '0';
 
 
 
  signal RX_Parity_Err       : std_logic := '0';
 
 
 
 
 
begin
 
begin
 
 
 
 
 
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
 
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
 
 
 
  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En;
 
 
 
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
 
 
 
 
 
  io_reg: process( Clock, Reset )
 
  io_reg: process( Clock, Reset )
 
  begin
 
  begin
 
    if( Reset = Reset_Level )then
 
    if( Reset = Reset_Level )then
 
      Rd_En                  <= '0';
 
      Reg_Sel_q              <= '0';
 
 
 
      Wr_En_q                <= '0';
 
 
 
      Wr_Data_q              <= x"00";
 
 
 
      Rd_En_q                <= '0';
 
      Rd_Data                <= OPEN8_NULLBUS;
 
      Rd_Data                <= OPEN8_NULLBUS;
 
      RTS_Out                <= '0';
 
      RTS_Out                <= '0';
 
 
 
      RX_Parity_Err          <= '0';
 
    elsif( rising_edge( Clock ) )then
 
    elsif( rising_edge( Clock ) )then
 
 
 
      Reg_Sel_q              <= Reg_Sel_d;
 
 
 
 
 
 
 
      Wr_En_q                <= Wr_En_d;
 
 
 
      Wr_Data_q              <= Wr_Data_d;
 
 
 
 
 
 
 
      TX_FIFO_Wr_En          <= Wr_En_q and not Reg_Sel_q;
 
 
 
      TX_FIFO_Wr_Data        <= Wr_Data_q;
 
 
 
 
 
 
 
      if( Rx_PErr = '1' )then
 
 
 
        RX_Parity_Err        <= '1';
 
 
 
      elsif( Wr_En_q = '1' and Reg_Sel_q = '1' and Write_Qual = '1' )then
 
 
 
        RX_Parity_Err        <= '0';
 
 
 
      end if;
 
 
 
 
 
 
 
      Rd_En_q                <= Rd_En_d;
 
      Rd_Data                <= OPEN8_NULLBUS;
 
      Rd_Data                <= OPEN8_NULLBUS;
 
      Rd_En                  <= Addr_Match and Open8_Bus.Rd_En;
 
      if( Rd_En_q = '1' and Reg_Sel_q = '1' )then
 
      Reg_Sel                <= Reg_Addr;
 
                  Rd_Data(3)           <= RX_Parity_Err;
 
      if( Rd_En = '1' and Reg_Sel = '1' )then
 
 
 
        Rd_Data(4)           <= RX_FIFO_Empty;
 
        Rd_Data(4)           <= RX_FIFO_Empty;
 
        Rd_Data(5)           <= RX_FIFO_AFull;
 
        Rd_Data(5)           <= RX_FIFO_AFull;
 
        Rd_Data(6)           <= TX_FIFO_Empty;
 
        Rd_Data(6)           <= TX_FIFO_Empty;
 
        Rd_Data(7)           <= TX_FIFO_AFull;
 
        Rd_Data(7)           <= TX_FIFO_AFull;
 
      end if;
 
      end if;
 
      if( Rd_En = '1' and Reg_Sel = '0' )then
 
      if( Rd_En_q = '1' and Reg_Sel_q = '0' )then
 
        Rd_Data              <= RX_FIFO_Rd_Data;
 
        Rd_Data              <= RX_FIFO_Rd_Data;
 
      end if;
 
      end if;
 
      RTS_Out                <= not RX_FIFO_AFull;
 
      RTS_Out                <= not RX_FIFO_AFull;
 
 
 
 
 
    end if;
 
    end if;
 
  end process;
 
  end process;
 
 
 
 
 
TX_Disabled : if( Disable_Transmit )generate
 
TX_Disabled : if( Disable_Transmit )generate
 
 
 
 
Line 157... Line 192... 
 
 
 
 
end generate;
 
end generate;
 
 
 
 
 
TX_Enabled : if( not Disable_Transmit )generate
 
TX_Enabled : if( not Disable_Transmit )generate
 
 
 
 
 
  TX_FIFO_Wr_En              <= Open8_Bus.Wr_En and
 
 
 
                                Addr_Match and
 
 
 
                                (not Reg_Addr);
 
 
 
 
 
 
 
  FIFO_Reset                 <= '1' when Reset = Reset_Level else '0';
 
  FIFO_Reset                 <= '1' when Reset = Reset_Level else '0';
 
 
 
 
 
  U_TX_FIFO : entity work.fifo_1k_core
 
  U_TX_FIFO : entity work.fifo_1k_core
 
  port map(
 
  port map(
 
    aclr                     => FIFO_Reset,
 
    aclr                     => FIFO_Reset,
Line 234... Line 265... 
    Tx_Done                  => Tx_Done
 
    Tx_Done                  => Tx_Done
 
  );
 
  );
 
 
 
 
 
end generate;
 
end generate;
 
 
 
 
 
RX_Disabled : if( Disable_Transmit )generate
 
RX_Disabled : if( Disable_Receive )generate
 
 
 
 
 
 
 
  Rx_PErr                    <= '0';
 
  RX_FIFO_Empty              <= '1';
 
  RX_FIFO_Empty              <= '1';
 
  RX_FIFO_AFull              <= '0';
 
  RX_FIFO_AFull              <= '0';
 
  RX_FIFO_Rd_Data            <= x"00";
 
  RX_FIFO_Rd_Data            <= x"00";
 
 
 
 
 
end generate;
 
end generate;
Line 259... Line 291... 
    --
 
    --
 
    Rx_In                    => RX_In,
 
    Rx_In                    => RX_In,
 
    --
 
    --
 
    Rx_Data                  => RX_FIFO_Wr_Data,
 
    Rx_Data                  => RX_FIFO_Wr_Data,
 
    Rx_Valid                 => RX_FIFO_Wr_En,
 
    Rx_Valid                 => RX_FIFO_Wr_En,
 
    Rx_PErr                  => open
 
    Rx_PErr                  => Rx_PErr
 
  );
 
  );
 
 
 
 
 
  RX_FIFO_Rd_En              <= Open8_Bus.Rd_En and
 
  RX_FIFO_Rd_En              <= Open8_Bus.Rd_En and
 
                                Addr_Match and
 
                                Addr_Match and
 
                                (not Reg_Addr);
 
                                (not Reg_Sel_d);
 
 
 
 
 
  U_RX_FIFO : entity work.fifo_1k_core
 
  U_RX_FIFO : entity work.fifo_1k_core
 
  port map(
 
  port map(
 
    aclr                     => FIFO_Reset,
 
    aclr                     => FIFO_Reset,
 
    clock                    => Clock,
 
    clock                    => Clock,

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