| Line 47... |
Line 47... |
------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 12/20/19 Design Start
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-- Seth Henry 12/20/19 Design Start
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-- Seth Henry 04/10/20 Code cleanup and register documentation
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-- Seth Henry 04/10/20 Code cleanup and register documentation
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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-- Seth Henry 05/18/20 Added write qualification input
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-- Seth Henry 05/18/20 Added write qualification input
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-- Seth Henry 6/06/23 Inverted flow control signals for standard EIA-232
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 73... |
Line 74... |
Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Write_Qual : in std_logic := '1';
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Write_Qual : in std_logic := '1';
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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--
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--
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TX_Out : out std_logic;
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TX_Out : out std_logic;
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CTS_In : in std_logic := '1';
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CTS_In : in std_logic := '0';
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RX_In : in std_logic := '1';
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RX_In : in std_logic := '1';
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RTS_Out : out std_logic
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RTS_Out : out std_logic
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);
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);
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end entity;
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end entity;
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| Line 177... |
Line 178... |
Rd_Data(7) <= TX_FIFO_AFull;
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Rd_Data(7) <= TX_FIFO_AFull;
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end if;
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end if;
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if( Rd_En_q = '1' and Reg_Sel_q = '0' )then
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if( Rd_En_q = '1' and Reg_Sel_q = '0' )then
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Rd_Data <= RX_FIFO_Rd_Data;
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Rd_Data <= RX_FIFO_Rd_Data;
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end if;
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end if;
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RTS_Out <= not RX_FIFO_AFull;
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RTS_Out <= RX_FIFO_AFull;
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end if;
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end if;
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end process;
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end process;
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TX_Disabled : if( Disable_Transmit )generate
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TX_Disabled : if( Disable_Transmit )generate
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| Line 216... |
Line 217... |
TX_FIFO_Rd_En <= '0';
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TX_FIFO_Rd_En <= '0';
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CTS_sr <= (others => '0');
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CTS_sr <= (others => '0');
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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TX_Xmit <= '0';
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TX_Xmit <= '0';
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TX_FIFO_Rd_En <= '0';
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TX_FIFO_Rd_En <= '0';
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CTS_sr <= CTS_sr(2 downto 0) & CTS_In;
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CTS_sr <= CTS_sr(2 downto 0) & (not CTS_In);
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case( TX_Ctrl )is
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case( TX_Ctrl )is
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when IDLE =>
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when IDLE =>
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if( TX_FIFO_Empty = '0' and CTS_Okay = '1' )then
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if( TX_FIFO_Empty = '0' and CTS_Okay = '1' )then
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TX_FIFO_Rd_En <= '1';
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TX_FIFO_Rd_En <= '1';
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