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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_async_serial.vhd] - Diff between revs 293 and 320

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Rev 293 Rev 320
Line 47... Line 47...
------------------ -------- ---------------------------------------------------
------------------ -------- ---------------------------------------------------
-- Seth Henry      12/20/19 Design Start
-- Seth Henry      12/20/19 Design Start
-- Seth Henry      04/10/20 Code cleanup and register documentation
-- Seth Henry      04/10/20 Code cleanup and register documentation
-- Seth Henry      04/16/20 Modified to use Open8 bus record
-- Seth Henry      04/16/20 Modified to use Open8 bus record
-- Seth Henry      05/18/20 Added write qualification input
-- Seth Henry      05/18/20 Added write qualification input
 
-- Seth Henry       6/06/23 Inverted flow control signals for standard EIA-232
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
Line 73... Line 74...
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Write_Qual                 : in  std_logic := '1';
  Write_Qual                 : in  std_logic := '1';
  Rd_Data                    : out DATA_TYPE;
  Rd_Data                    : out DATA_TYPE;
  --
  --
  TX_Out                     : out std_logic;
  TX_Out                     : out std_logic;
  CTS_In                     : in  std_logic := '1';
  CTS_In                     : in  std_logic := '0';
  RX_In                      : in  std_logic := '1';
  RX_In                      : in  std_logic := '1';
  RTS_Out                    : out std_logic
  RTS_Out                    : out std_logic
);
);
end entity;
end entity;
 
 
Line 177... Line 178...
        Rd_Data(7)           <= TX_FIFO_AFull;
        Rd_Data(7)           <= TX_FIFO_AFull;
      end if;
      end if;
      if( Rd_En_q = '1' and Reg_Sel_q = '0' )then
      if( Rd_En_q = '1' and Reg_Sel_q = '0' )then
        Rd_Data              <= RX_FIFO_Rd_Data;
        Rd_Data              <= RX_FIFO_Rd_Data;
      end if;
      end if;
      RTS_Out                <= not RX_FIFO_AFull;
      RTS_Out                <= RX_FIFO_AFull;
 
 
    end if;
    end if;
  end process;
  end process;
 
 
TX_Disabled : if( Disable_Transmit )generate
TX_Disabled : if( Disable_Transmit )generate
Line 216... Line 217...
      TX_FIFO_Rd_En          <= '0';
      TX_FIFO_Rd_En          <= '0';
      CTS_sr                 <= (others => '0');
      CTS_sr                 <= (others => '0');
    elsif( rising_edge(Clock) )then
    elsif( rising_edge(Clock) )then
      TX_Xmit                <= '0';
      TX_Xmit                <= '0';
      TX_FIFO_Rd_En          <= '0';
      TX_FIFO_Rd_En          <= '0';
      CTS_sr                 <= CTS_sr(2 downto 0) & CTS_In;
      CTS_sr                 <= CTS_sr(2 downto 0) & (not CTS_In);
 
 
      case( TX_Ctrl )is
      case( TX_Ctrl )is
        when IDLE =>
        when IDLE =>
          if( TX_FIFO_Empty = '0' and CTS_Okay = '1' )then
          if( TX_FIFO_Empty = '0' and CTS_Okay = '1' )then
            TX_FIFO_Rd_En    <= '1';
            TX_FIFO_Rd_En    <= '1';

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