OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_btn_int.vhd] - Diff between revs 217 and 223

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 217 Rev 223
Line 53... Line 53...
port(
port(
  Clock                      : in  std_logic := '0';
  Clock                      : in  std_logic := '0';
  Reset                      : in  std_logic := '0';
  Reset                      : in  std_logic := '0';
  uSec_Tick                  : in  std_logic := '0';
  uSec_Tick                  : in  std_logic := '0';
  --
  --
  Bus_Address                : in  ADDRESS_TYPE := x"0000";
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Rd_Enable                  : in  std_logic := '0';
 
  Rd_Data                    : out DATA_TYPE;
  Rd_Data                    : out DATA_TYPE;
  Interrupt                  : out std_logic;
  Interrupt                  : out std_logic;
  --
  --
  Button_In                  : in  DATA_TYPE := x"00"
  Button_In                  : in  DATA_TYPE := x"00"
);
);
end entity;
end entity;
 
 
architecture behave of o8_btn_int is
architecture behave of o8_btn_int is
 
 
  constant User_Addr         : std_logic_vector(15 downto 0) := Address;
  constant User_Addr         : std_logic_vector(15 downto 0) := Address;
  alias  Comp_Addr           is Bus_Address(15 downto 0);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 0);
  signal Addr_Match          : std_logic  := '0';
  signal Addr_Match          : std_logic  := '0';
  signal Rd_En               : std_logic  := '0';
  signal Rd_En               : std_logic  := '0';
 
 
  constant MSEC_DELAY        : std_logic_vector(9 downto 0) :=
  constant MSEC_DELAY        : std_logic_vector(9 downto 0) :=
                                conv_std_logic_vector(1000,10);
                                conv_std_logic_vector(1000,10);
Line 80... Line 79...
  signal Button_Pressed      : DATA_TYPE := x"00";
  signal Button_Pressed      : DATA_TYPE := x"00";
  signal Button_CoS          : DATA_TYPE := x"00";
  signal Button_CoS          : DATA_TYPE := x"00";
 
 
begin
begin
 
 
  Addr_Match                 <= Rd_Enable when Comp_Addr = User_Addr else '0';
  Addr_Match                 <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else
 
                                '0';
 
 
  io_reg: process( Clock, Reset )
  io_reg: process( Clock, Reset )
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      Rd_En                  <= '0';
      Rd_En                  <= '0';

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.