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-- VHDL Units : o8_clk_detect
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-- VHDL Units : o8_clk_detect
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-- Description: Provides up/down status and interrupt for monitoring a clock
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-- Description: Provides up/down status and interrupt for monitoring a clock
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--
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--
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-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x00 BB-----A VSD Engine PLL Reset (RO/RW)
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-- 0x00 BA------ VSD Engine PLL Reset (RO/RW)
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-- A = Interrupt Enable (1 = enabled, 0 = masked) (RW)
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-- A = Clock Line State (follows input) (RO)
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-- B = Clock Line State (follows input, only valid if B = 1) (RO)
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-- B = Clock Detect (1 = transition detected) (RO)
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-- C = Clock Detect (1 = transition detected) (RO)
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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Line 50... |
Reset : in std_logic;
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Reset : in std_logic;
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--
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--
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Ref_Clk_In : in std_logic;
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Ref_Clk_In : in std_logic;
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--
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--
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Bus_Address : in ADDRESS_TYPE;
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Bus_Address : in ADDRESS_TYPE;
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Wr_Enable : in std_logic;
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Wr_Data : in DATA_TYPE;
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Rd_Enable : in std_logic;
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Rd_Enable : in std_logic;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic
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Interrupt : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_clk_detect is
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architecture behave of o8_clk_detect is
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constant User_Addr : std_logic_vector(15 downto 0) := Address;
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constant User_Addr : std_logic_vector(15 downto 0) := Address;
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alias Comp_Addr is Bus_Address(15 downto 0);
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alias Comp_Addr is Bus_Address(15 downto 0);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic := '0';
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signal Wr_Data_Q : DATA_TYPE;
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signal Rd_En : std_logic := '0';
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signal Wr_En : std_logic;
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signal Rd_En : std_logic;
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signal Int_En : std_logic;
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function ceil_log2 (x : in natural) return natural is
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variable retval : natural;
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begin
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retval := 1;
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while ((2**retval) - 1) < x loop
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retval := retval + 1;
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end loop;
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return retval;
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end function;
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constant Threshold_bits : integer := ceil_log2(Threshold_Count);
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constant Threshold_bits : integer := ceil_log2(Threshold_Count);
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constant THRESHOLD : std_logic_vector(Threshold_bits - 1 downto 0) :=
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constant THRESHOLD : std_logic_vector(Threshold_bits - 1 downto 0) :=
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conv_std_logic_vector(Threshold_Count,Threshold_bits);
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conv_std_logic_vector(Threshold_Count,Threshold_bits);
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signal RE_Threshold_Ctr : std_logic_vector(Threshold_Bits - 1 downto 0);
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signal RE_Threshold_Ctr : std_logic_vector(Threshold_Bits - 1 downto 0) :=
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signal FE_Threshold_Ctr : std_logic_vector(Threshold_Bits - 1 downto 0);
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(others => '0');
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signal FE_Threshold_Ctr : std_logic_vector(Threshold_Bits - 1 downto 0) :=
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(others => '0');
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signal Ref_In_SR : std_logic_vector(3 downto 0);
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signal Ref_In_SR : std_logic_vector(3 downto 0) := (others => '0');
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alias Ref_In_q1 is Ref_In_SR(2);
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alias Ref_In_q1 is Ref_In_SR(2);
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alias Ref_In_q2 is Ref_In_SR(3);
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alias Ref_In_q2 is Ref_In_SR(3);
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signal Ref_In_RE : std_logic;
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signal Ref_In_RE : std_logic := '0';
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signal Ref_In_FE : std_logic;
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signal Ref_In_FE : std_logic := '0';
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signal Ref_Detect : std_logic;
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signal Ref_Detect : std_logic := '0';
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signal Ref_Detect_q1 : std_logic;
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signal Ref_Detect_q1 : std_logic := '0';
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signal Ref_Detect_CoS : std_logic;
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signal Ref_Detect_CoS : std_logic := '0';
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= Rd_Enable when Comp_Addr = User_Addr else '0';
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Wr_Data_Q <= x"00";
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Wr_En <= '0';
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= x"00";
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Rd_Data <= OPEN8_NULLBUS;
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Int_En <= '0';
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Wr_Data_Q <= Wr_Data;
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Rd_En <= Addr_Match;
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Wr_En <= Wr_Enable and Addr_Match;
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Rd_En <= Rd_Enable and Addr_Match;
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if( Wr_En = '1' )then
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Int_En <= Wr_Data_Q(0);
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end if;
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Rd_Data <= (others => '0');
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Rd_Data <= OPEN8_NULLBUS;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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Rd_Data(0) <= Int_En;
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Rd_Data(6) <= Ref_In_q2;
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Rd_Data(6) <= Ref_In_q2;
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Rd_Data(7) <= Ref_Detect;
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Rd_Data(7) <= Ref_Detect;
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end if;
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end if;
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end if;
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end if;
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Ref_Detect <= or_reduce(RE_Threshold_Ctr) and
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Ref_Detect <= or_reduce(RE_Threshold_Ctr) and
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or_reduce(FE_Threshold_Ctr);
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or_reduce(FE_Threshold_Ctr);
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Ref_Detect_q1 <= Ref_Detect;
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Ref_Detect_q1 <= Ref_Detect;
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Ref_Detect_CoS <= Ref_Detect xor Ref_Detect_q1;
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Ref_Detect_CoS <= Ref_Detect xor Ref_Detect_q1;
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Interrupt <= Ref_Detect_CoS and Int_En;
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Interrupt <= Ref_Detect_CoS;
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end if;
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end if;
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end process;
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end process;
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end architecture;
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end architecture;
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