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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_clk_detect.vhd] - Diff between revs 194 and 197

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Rev 194 Rev 197
Line 24... Line 24...
-- VHDL Units :  o8_clk_detect
-- VHDL Units :  o8_clk_detect
-- Description:  Provides up/down status and interrupt for monitoring a clock
-- Description:  Provides up/down status and interrupt for monitoring a clock
--
--
-- Register Map:
-- Register Map:
-- Offset  Bitfield Description                          Read/Write
-- Offset  Bitfield Description                          Read/Write
--   0x00   BA------ VSD Engine PLL Reset                (RO/RW)
--  0x00   BA------ Recieve Clock Status                   (RO)
--                    A = Clock Line State (follows input) (RO)
--                    A = Clock Line State (follows input)
--                    B = Clock Detect (1 = transition detected) (RO)
--                    B = Clock Detect (1 = transition detected)
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;

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