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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_clk_detect.vhd] - Diff between revs 194 and 197
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| Rev 194 |
Rev 197 |
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-- VHDL Units : o8_clk_detect
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-- VHDL Units : o8_clk_detect
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-- Description: Provides up/down status and interrupt for monitoring a clock
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-- Description: Provides up/down status and interrupt for monitoring a clock
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--
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--
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-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x00 BA------ VSD Engine PLL Reset (RO/RW)
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-- 0x00 BA------ Recieve Clock Status (RO)
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-- A = Clock Line State (follows input) (RO)
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-- A = Clock Line State (follows input)
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-- B = Clock Detect (1 = transition detected) (RO)
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-- B = Clock Detect (1 = transition detected)
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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