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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_clk_detect.vhd] - Diff between revs 217 and 223
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| Rev 217 |
Rev 223 |
| Line 49... |
Line 49... |
Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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--
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--
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Ref_Clk_In : in std_logic;
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Ref_Clk_In : in std_logic;
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--
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--
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Bus_Address : in ADDRESS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Enable : in std_logic;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic
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Interrupt : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_clk_detect is
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architecture behave of o8_clk_detect is
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constant User_Addr : std_logic_vector(15 downto 0) := Address;
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constant User_Addr : std_logic_vector(15 downto 0) := Address;
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alias Comp_Addr is Bus_Address(15 downto 0);
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alias Comp_Addr is Open8_Bus.Address(15 downto 0);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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signal Rd_En : std_logic := '0';
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signal Rd_En : std_logic := '0';
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constant Threshold_bits : integer := ceil_log2(Threshold_Count);
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constant Threshold_bits : integer := ceil_log2(Threshold_Count);
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| Line 85... |
Line 84... |
signal Ref_Detect_q1 : std_logic := '0';
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signal Ref_Detect_q1 : std_logic := '0';
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signal Ref_Detect_CoS : std_logic := '0';
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signal Ref_Detect_CoS : std_logic := '0';
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begin
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begin
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Addr_Match <= Rd_Enable when Comp_Addr = User_Addr else '0';
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Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else '0';
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Rd_En <= '0';
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Rd_En <= '0';
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