| Line 27... |
Line 27... |
-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x00 BA------ Recieve Clock Status (RO)
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-- 0x00 BA------ Recieve Clock Status (RO)
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-- A = Clock Line State (follows input)
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-- A = Clock Line State (follows input)
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-- B = Clock Detect (1 = transition detected)
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-- B = Clock Detect (1 = transition detected)
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--
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-- Revision History
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 04/16/20 Revision block added
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 40... |
Line 45... |
use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_clk_detect is
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entity o8_clk_detect is
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generic(
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generic(
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Threshold_Count : integer;
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Threshold_Count : integer;
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Address : ADDRESS_TYPE;
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Address : ADDRESS_TYPE
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Reset_Level : std_logic
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);
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);
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port(
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port(
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Clock : in std_logic;
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Reset : in std_logic;
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--
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Ref_Clk_In : in std_logic;
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Ref_Clk_In : in std_logic;
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--
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--
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic
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Interrupt : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_clk_detect is
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architecture behave of o8_clk_detect is
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|
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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constant User_Addr : std_logic_vector(15 downto 0) := Address;
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constant User_Addr : std_logic_vector(15 downto 0) := Address;
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alias Comp_Addr is Open8_Bus.Address(15 downto 0);
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alias Comp_Addr is Open8_Bus.Address(15 downto 0);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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|
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signal Rd_En : std_logic := '0';
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signal Rd_En : std_logic := '0';
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