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Line 65... |
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constant User_Addr : std_logic_vector(15 downto 0) := Address;
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constant User_Addr : std_logic_vector(15 downto 0) := Address;
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alias Comp_Addr is Open8_Bus.Address(15 downto 0);
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alias Comp_Addr is Open8_Bus.Address(15 downto 0);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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signal Rd_En : std_logic := '0';
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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constant Threshold_bits : integer := ceil_log2(Threshold_Count);
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constant Threshold_bits : integer := ceil_log2(Threshold_Count);
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constant THRESHOLD : std_logic_vector(Threshold_bits - 1 downto 0) :=
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constant THRESHOLD : std_logic_vector(Threshold_bits - 1 downto 0) :=
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conv_std_logic_vector(Threshold_Count,Threshold_bits);
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conv_std_logic_vector(Threshold_Count,Threshold_bits);
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Line 89... |
signal Ref_Detect_q1 : std_logic := '0';
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signal Ref_Detect_q1 : std_logic := '0';
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signal Ref_Detect_CoS : std_logic := '0';
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signal Ref_Detect_CoS : std_logic := '0';
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begin
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begin
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Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Rd_En <= '0';
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Rd_En_q <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Rd_En <= Addr_Match;
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Rd_En_q <= Rd_En_d;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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if( Rd_En = '1' )then
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if( Rd_En_q = '1' )then
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Rd_Data(6) <= Ref_In_q2;
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Rd_Data(6) <= Ref_In_q2;
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Rd_Data(7) <= Ref_Detect;
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Rd_Data(7) <= Ref_Detect;
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end if;
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end if;
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end if;
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end if;
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