| Line 71... |
Line 71... |
-- :
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-- :
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 07/19/06 Design Start
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-- Seth Henry 07/19/06 Design Start
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-- Seth Henry 01/18/11 Fixed BTT instruction to match V8
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 91... |
Line 92... |
Default_Interrupt_Mask : DATA_TYPE := x"FF"; -- Enable all Ints
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Default_Interrupt_Mask : DATA_TYPE := x"FF"; -- Enable all Ints
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Enable_CPU_Halt : std_logic := '0'; -- Disable HALT pin
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Enable_CPU_Halt : std_logic := '0'; -- Disable HALT pin
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Enable_Auto_Increment : std_logic := '0' ); -- Modify indexed instr
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Enable_Auto_Increment : std_logic := '0' ); -- Modify indexed instr
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset_n : in std_logic;
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Reset : in std_logic;
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CPU_Halt : in std_logic;
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CPU_Halt : in std_logic;
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Interrupts : in INTERRUPT_BUNDLE;
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Interrupts : in INTERRUPT_BUNDLE;
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--
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--
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Address : out ADDRESS_TYPE;
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Address : out ADDRESS_TYPE;
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Rd_Data : in DATA_TYPE;
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Rd_Data : in DATA_TYPE;
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| Line 131... |
Line 132... |
constant ALU_UPP : OPCODE_TYPE := "11000"; -- x"18"
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constant ALU_UPP : OPCODE_TYPE := "11000"; -- x"18"
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constant ALU_LDI : OPCODE_TYPE := "11100"; -- x"1C"
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constant ALU_LDI : OPCODE_TYPE := "11100"; -- x"1C"
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constant ALU_LDX : OPCODE_TYPE := "11110"; -- x"1E"
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constant ALU_LDX : OPCODE_TYPE := "11110"; -- x"1E"
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constant ALU_IDLE : OPCODE_TYPE := "10000"; -- x"10"
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constant ALU_IDLE : OPCODE_TYPE := "10000"; -- x"10"
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constant ALU_UPP2 : OPCODE_TYPE := "10010"; -- x"11"
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constant ALU_UPP2 : OPCODE_TYPE := "10010"; -- x"12"
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constant ALU_RFLG : OPCODE_TYPE := "10011"; -- x"12"
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constant ALU_RFLG : OPCODE_TYPE := "10011"; -- x"13"
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constant FL_ZERO : integer := 0;
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constant FL_ZERO : integer := 0;
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constant FL_CARRY : integer := 1;
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constant FL_CARRY : integer := 1;
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constant FL_NEG : integer := 2;
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constant FL_NEG : integer := 2;
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constant FL_INT_EN : integer := 3;
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constant FL_INT_EN : integer := 3;
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| Line 384... |
Line 385... |
Flags_D(FL_NEG) <= Sum(7);
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Flags_D(FL_NEG) <= Sum(7);
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when ALU_STP => -- Sets bit(n) in the Flags register
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when ALU_STP => -- Sets bit(n) in the Flags register
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Flags_D(Index) <= '1';
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Flags_D(Index) <= '1';
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when ALU_BTT => -- Tests if R0 is negative or zero. No change to R0
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when ALU_BTT => -- Z = !R0(N), N = R0(7)
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Temp := "0" & Regfile(Index);
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Flags_D(FL_ZERO) <= not Regfile(0)(Index);
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Flags_D(FL_ZERO) <= '0';
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Flags_D(FL_NEG) <= Regfile(0)(7);
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if( Temp(7 downto 0) = 0 )then
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-- Temp := "0" & Regfile(Index);
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Flags_D(FL_ZERO) <= '1';
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-- Flags_D(FL_ZERO) <= '0';
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end if;
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-- if( Temp(7 downto 0) = 0 )then
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Flags_D(FL_NEG) <= Temp(7);
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-- Flags_D(FL_ZERO) <= '1';
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-- end if;
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-- Flags_D(FL_NEG) <= Temp(7);
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when ALU_CLP => -- Clears bit(n) in the Flags register
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when ALU_CLP => -- Clears bit(n) in the Flags register
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Flags_D(Index) <= '0';
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Flags_D(Index) <= '0';
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when ALU_T0X => -- Rn = R0 : Flags N,Z
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when ALU_T0X => -- Rn = R0 : Flags N,Z
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| Line 415... |
Line 418... |
Flags_D(FL_ZERO) <= '1';
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Flags_D(FL_ZERO) <= '1';
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end if;
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end if;
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Flags_D(FL_CARRY) <= Sum(8);
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Flags_D(FL_CARRY) <= Sum(8);
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Flags_D(FL_NEG) <= Sum(7);
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Flags_D(FL_NEG) <= Sum(7);
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when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags N,Z
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when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
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Regfile_D(0) <= Mult(7 downto 0);
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Regfile_D(0) <= Mult(7 downto 0);
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Regfile_D(1) <= Mult(15 downto 8);
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Regfile_D(1) <= Mult(15 downto 8);
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Flags_D(FL_ZERO) <= '0';
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Flags_D(FL_ZERO) <= '0';
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if( Mult = 0 )then
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if( Mult = 0 )then
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Flags_D(FL_ZERO) <= '1';
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Flags_D(FL_ZERO) <= '1';
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| Line 462... |
Line 465... |
Mult <= Regfile(0) *
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Mult <= Regfile(0) *
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Regfile(conv_integer(ALU_Ctrl.Reg));
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Regfile(conv_integer(ALU_Ctrl.Reg));
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end if;
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end if;
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end process;
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end process;
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S_Regs: process( Reset_n, Clock )
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S_Regs: process( Reset, Clock )
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begin
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begin
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if( Reset_n = '0' )then
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if( Reset = '1' )then
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for i in 0 to 7 loop
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for i in 0 to 7 loop
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Regfile(i) <= (others => '0');
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Regfile(i) <= (others => '0');
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end loop;
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end loop;
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Flags <= x"00";
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Flags <= x"00";
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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| Line 501... |
Line 504... |
if( PC_Ctrl.Oper = PC_REV2 )then
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if( PC_Ctrl.Oper = PC_REV2 )then
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Rewind_1_2n <= '0';
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Rewind_1_2n <= '0';
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end if;
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end if;
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end process;
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end process;
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Program_Counter: process( Reset_n, Clock, Halt, PC_Ctrl, PC_Q, Rewind_1_2n )
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Program_Counter: process( Reset, Clock, Halt, PC_Ctrl, PC_Q, Rewind_1_2n )
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variable PC_Offset_SX : ADDRESS_TYPE := x"0000";
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variable PC_Offset_SX : ADDRESS_TYPE := x"0000";
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begin
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begin
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PC_Offset_SX(15 downto 8):= (others => PC_Ctrl.Offset(7));
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PC_Offset_SX(15 downto 8):= (others => PC_Ctrl.Offset(7));
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PC_Offset_SX(7 downto 0) := PC_Ctrl.Offset;
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PC_Offset_SX(7 downto 0) := PC_Ctrl.Offset;
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if( Reset_n = '0' )then
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if( Reset = '1' )then
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PC_Q <= Program_Start_Addr;
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PC_Q <= Program_Start_Addr;
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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if( Halt = '0' )then
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if( Halt = '0' )then
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case PC_Ctrl.Oper is
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case PC_Ctrl.Oper is
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when PC_IDLE =>
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when PC_IDLE =>
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| Line 537... |
Line 540... |
signal SP_Q : ADDRESS_TYPE := (others => '0');
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signal SP_Q : ADDRESS_TYPE := (others => '0');
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begin
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begin
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SP <= SP_Q;
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SP <= SP_Q;
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Stack_Pointer: process( Reset_n, Clock )
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Stack_Pointer: process( Reset, Clock )
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begin
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begin
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if( Reset_n = '0' )then
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if( Reset = '1' )then
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SP_Q <= Stack_Start_Addr;
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SP_Q <= Stack_Start_Addr;
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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if( Halt = '0' )then
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if( Halt = '0' )then
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case SP_Ctrl.Oper is
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case SP_Ctrl.Oper is
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when SP_IDLE => null;
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when SP_IDLE => null;
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| Line 664... |
Line 667... |
Int_Trig <= '1';
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Int_Trig <= '1';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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S_Regs: process( Reset_n, Clock )
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S_Regs: process( Reset, Clock )
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begin
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begin
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if( Reset_n = '0' )then
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if( Reset = '1' )then
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Int_Req <= '0';
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Int_Req <= '0';
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Pending <= x"00";
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Pending <= x"00";
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Wait_for_FSM <= '0';
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Wait_for_FSM <= '0';
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Mask <= Default_Interrupt_Mask(7 downto 1);
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Mask <= Default_Interrupt_Mask(7 downto 1);
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ISR_Q <= INT_VECTOR_0;
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ISR_Q <= INT_VECTOR_0;
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| Line 1323... |
Line 1326... |
end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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S_Regs: process( Reset_n, Clock )
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S_Regs: process( Reset, Clock )
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begin
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begin
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if( Reset_n = '0' )then
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if( Reset = '1' )then
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CPU_State <= PIPE_FILL_0;
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CPU_State <= PIPE_FILL_0;
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Opcode <= OP_INC;
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Opcode <= OP_INC;
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SubOp <= ACCUM;
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SubOp <= ACCUM;
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SubOp_p1 <= ACCUM;
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SubOp_p1 <= ACCUM;
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Operand1 <= x"00";
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Operand1 <= x"00";
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| Line 1473... |
Line 1476... |
for i in 0 to 7 loop
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for i in 0 to 7 loop
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Wr_Data_D(i) <= Reg_Mux(i) or Flag_Mux(i) or PC_Mux(i);
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Wr_Data_D(i) <= Reg_Mux(i) or Flag_Mux(i) or PC_Mux(i);
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end loop;
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end loop;
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end process;
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end process;
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S_Regs: process( Reset_n, Clock )
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S_Regs: process( Reset, Clock )
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begin
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begin
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if( Reset_n = '0' )then
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if( Reset = '1' )then
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Wr_Data <= (others => '0');
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Wr_Data <= (others => '0');
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Wr_Enable <= '0';
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Wr_Enable <= '0';
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Rd_Enable <= '1';
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Rd_Enable <= '1';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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if( Halt = '0' )then
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if( Halt = '0' )then
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| Line 1492... |
Line 1495... |
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end block;
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end block;
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end rtl;
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end rtl;
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