| Line 505... |
Line 505... |
if( PC_Ctrl.Oper = PC_REV2 )then
|
if( PC_Ctrl.Oper = PC_REV2 )then
|
Rewind_1_2n <= '0';
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Rewind_1_2n <= '0';
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end if;
|
end if;
|
end process;
|
end process;
|
|
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Program_Counter: process( Reset, Clock, PC_Ctrl )
|
Program_Counter: process( Reset, Clock, Halt, PC_Ctrl, PC_Q, Rewind_1_2n )
|
variable PC_Offset_SX : ADDRESS_TYPE := x"0000";
|
variable PC_Offset_SX : ADDRESS_TYPE := x"0000";
|
begin
|
begin
|
PC_Offset_SX(15 downto 8):= (others => PC_Ctrl.Offset(7));
|
PC_Offset_SX(15 downto 8):= (others => PC_Ctrl.Offset(7));
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PC_Offset_SX(7 downto 0) := PC_Ctrl.Offset;
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PC_Offset_SX(7 downto 0) := PC_Ctrl.Offset;
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
| Line 1239... |
Line 1239... |
|
|
when ISR_C1 =>
|
when ISR_C1 =>
|
CPU_Next_State <= ISR_C2;
|
CPU_Next_State <= ISR_C2;
|
AS_Ctrl.Src <= ADDR_ISR;
|
AS_Ctrl.Src <= ADDR_ISR;
|
INT_Ctrl.Incr_ISR <= '1';
|
INT_Ctrl.Incr_ISR <= '1';
|
-- PC_Ctrl.Oper <= PC_INCR;
|
|
-- Rewind the PC by 3 to compensate for the pipeline registers
|
|
-- PC_Ctrl.Offset <= x"FF";
|
|
|
|
when ISR_C2 =>
|
when ISR_C2 =>
|
CPU_Next_State <= ISR_C3;
|
CPU_Next_State <= ISR_C3;
|
AS_Ctrl.Src <= ADDR_ISR;
|
AS_Ctrl.Src <= ADDR_ISR;
|
DP_Ctrl.Src <= DATA_FLAG;
|
DP_Ctrl.Src <= DATA_FLAG;
|
| Line 1333... |
Line 1330... |
-- Reset all of the sub-block controls to IDLE, to avoid unintended
|
-- Reset all of the sub-block controls to IDLE, to avoid unintended
|
-- operation due to the current instruction
|
-- operation due to the current instruction
|
ALU_Ctrl.Oper <= ALU_IDLE;
|
ALU_Ctrl.Oper <= ALU_IDLE;
|
Cache_Ctrl <= CACHE_IDLE;
|
Cache_Ctrl <= CACHE_IDLE;
|
SP_Ctrl.Oper <= SP_IDLE;
|
SP_Ctrl.Oper <= SP_IDLE;
|
|
DP_Ctrl.Src <= DATA_IDLE; -- JSH 7/20
|
-- Rewind the PC by 3 to compensate for the pipeline registers
|
-- Rewind the PC by 3 to compensate for the pipeline registers
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= x"FF";
|
PC_Ctrl.Offset <= x"FF";
|
CPU_Next_State <= ISR_C1;
|
CPU_Next_State <= ISR_C1;
|
|
|
