| Line 76... |
Line 76... |
-- Seth Henry 01/18/11 Fixed BTT instruction to match V8
|
-- Seth Henry 01/18/11 Fixed BTT instruction to match V8
|
-- Seth Henry 07/22/11 Fixed interrupt transition logic to avoid data
|
-- Seth Henry 07/22/11 Fixed interrupt transition logic to avoid data
|
-- corruption issues.
|
-- corruption issues.
|
-- Seth Henry 07/26/11 Optimized logic in ALU, stack pointer, and data path
|
-- Seth Henry 07/26/11 Optimized logic in ALU, stack pointer, and data path
|
-- sections.
|
-- sections.
|
|
-- Seth Henry 07/27/11 Optimized logic for timing, merged blocks into
|
|
-- single entity.
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
| Line 108... |
Line 110... |
Rd_Enable : out std_logic;
|
Rd_Enable : out std_logic;
|
Wr_Data : out DATA_TYPE;
|
Wr_Data : out DATA_TYPE;
|
Wr_Enable : out std_logic );
|
Wr_Enable : out std_logic );
|
end entity;
|
end entity;
|
|
|
architecture rtl of Open8_CPU is
|
architecture behave of Open8_CPU is
|
|
|
subtype OPCODE_TYPE is std_logic_vector(4 downto 0);
|
subtype OPCODE_TYPE is std_logic_vector(4 downto 0);
|
subtype SUBOP_TYPE is std_logic_vector(2 downto 0);
|
subtype SUBOP_TYPE is std_logic_vector(2 downto 0);
|
|
|
|
-- These are all the primary instructions/op-codes (upper 5-bits)
|
|
constant OP_INC : OPCODE_TYPE := "00000";
|
|
constant OP_ADC : OPCODE_TYPE := "00001";
|
|
constant OP_TX0 : OPCODE_TYPE := "00010";
|
|
constant OP_OR : OPCODE_TYPE := "00011";
|
|
constant OP_AND : OPCODE_TYPE := "00100";
|
|
constant OP_XOR : OPCODE_TYPE := "00101";
|
|
constant OP_ROL : OPCODE_TYPE := "00110";
|
|
constant OP_ROR : OPCODE_TYPE := "00111";
|
|
constant OP_DEC : OPCODE_TYPE := "01000";
|
|
constant OP_SBC : OPCODE_TYPE := "01001";
|
|
constant OP_ADD : OPCODE_TYPE := "01010";
|
|
constant OP_STP : OPCODE_TYPE := "01011";
|
|
constant OP_BTT : OPCODE_TYPE := "01100";
|
|
constant OP_CLP : OPCODE_TYPE := "01101";
|
|
constant OP_T0X : OPCODE_TYPE := "01110";
|
|
constant OP_CMP : OPCODE_TYPE := "01111";
|
|
constant OP_PSH : OPCODE_TYPE := "10000";
|
|
constant OP_POP : OPCODE_TYPE := "10001";
|
|
constant OP_BR0 : OPCODE_TYPE := "10010";
|
|
constant OP_BR1 : OPCODE_TYPE := "10011";
|
|
constant OP_DBNZ : OPCODE_TYPE := "10100"; -- USR
|
|
constant OP_INT : OPCODE_TYPE := "10101";
|
|
constant OP_MUL : OPCODE_TYPE := "10110"; -- USR2
|
|
constant OP_STK : OPCODE_TYPE := "10111";
|
|
constant OP_UPP : OPCODE_TYPE := "11000";
|
|
constant OP_STA : OPCODE_TYPE := "11001";
|
|
constant OP_STX : OPCODE_TYPE := "11010";
|
|
constant OP_STO : OPCODE_TYPE := "11011";
|
|
constant OP_LDI : OPCODE_TYPE := "11100";
|
|
constant OP_LDA : OPCODE_TYPE := "11101";
|
|
constant OP_LDX : OPCODE_TYPE := "11110";
|
|
constant OP_LDO : OPCODE_TYPE := "11111";
|
|
|
|
-- These are all specific sub-opcodes for OP_STK / 0xB8 (lower 3-bits)
|
|
constant SOP_RSP : SUBOP_TYPE := "000";
|
|
constant SOP_RTS : SUBOP_TYPE := "001";
|
|
constant SOP_RTI : SUBOP_TYPE := "010";
|
|
constant SOP_BRK : SUBOP_TYPE := "011";
|
|
constant SOP_JMP : SUBOP_TYPE := "100";
|
|
constant SOP_SMSK : SUBOP_TYPE := "101";
|
|
constant SOP_GMSK : SUBOP_TYPE := "110";
|
|
constant SOP_JSR : SUBOP_TYPE := "111";
|
|
|
|
-- Preinitialization is for simulation only - check actual reset conditions
|
|
type CPU_STATES is (
|
|
-- Instruction fetch & Decode
|
|
PIPE_FILL_0, PIPE_FILL_1, PIPE_FILL_2, INSTR_DECODE,
|
|
-- Branching
|
|
BRN_C1, DBNZ_C1, JMP_C1, JMP_C2,
|
|
-- Loads
|
|
LDA_C1, LDA_C2, LDA_C3, LDA_C4, LDI_C1, LDO_C1, LDX_C1, LDX_C2, LDX_C3,
|
|
-- Stores
|
|
STA_C1, STA_C2, STA_C3, STO_C1, STO_C2, STX_C1, STX_C2,
|
|
-- 2-cycle math
|
|
MUL_C1, UPP_C1,
|
|
-- Stack
|
|
PSH_C1, POP_C1, POP_C2, POP_C3, POP_C4,
|
|
-- Subroutines & Interrupts
|
|
WAIT_FOR_INT, ISR_C1, ISR_C2, ISR_C3, JSR_C1, JSR_C2,
|
|
RTS_C1, RTS_C2, RTS_C3, RTS_C4, RTS_C5, RTI_C6,
|
|
-- Debugging
|
|
BRK_C1 );
|
|
|
|
type CACHE_MODES is (CACHE_IDLE, CACHE_INSTR, CACHE_OPER1, CACHE_OPER2,
|
|
CACHE_PREFETCH );
|
|
|
|
type PC_MODES is ( PC_IDLE, PC_REV1, PC_REV2, PC_INCR, PC_LOAD );
|
|
|
|
type PC_CTRL_TYPE is record
|
|
Oper : PC_MODES;
|
|
Offset : DATA_TYPE;
|
|
Addr : ADDRESS_TYPE;
|
|
end record;
|
|
|
|
type SP_MODES is ( SP_IDLE, SP_RSET, SP_POP, SP_PUSH );
|
|
|
|
type SP_CTRL_TYPE is record
|
|
Oper : SP_MODES;
|
|
Addr : ADDRESS_TYPE;
|
|
end record;
|
|
|
|
type DP_MODES is ( DATA_IDLE, DATA_REG, DATA_FLAG, DATA_PC );
|
|
|
|
type DATA_CTRL_TYPE is record
|
|
Src : DP_MODES;
|
|
Reg : SUBOP_TYPE;
|
|
end record;
|
|
|
|
-- Preinitialization is for simulation only - check actual reset conditions
|
|
constant INT_VECTOR_0 : ADDRESS_TYPE := ISR_Start_Addr;
|
|
constant INT_VECTOR_1 : ADDRESS_TYPE := ISR_Start_Addr+2;
|
|
constant INT_VECTOR_2 : ADDRESS_TYPE := ISR_Start_Addr+4;
|
|
constant INT_VECTOR_3 : ADDRESS_TYPE := ISR_Start_Addr+6;
|
|
constant INT_VECTOR_4 : ADDRESS_TYPE := ISR_Start_Addr+8;
|
|
constant INT_VECTOR_5 : ADDRESS_TYPE := ISR_Start_Addr+10;
|
|
constant INT_VECTOR_6 : ADDRESS_TYPE := ISR_Start_Addr+12;
|
|
constant INT_VECTOR_7 : ADDRESS_TYPE := ISR_Start_Addr+14;
|
|
|
|
type INT_CTRL_TYPE is record
|
|
Mask_Set : std_logic;
|
|
Soft_Ints : INTERRUPT_BUNDLE;
|
|
Incr_ISR : std_logic;
|
|
end record;
|
|
|
|
type INT_HIST is array (0 to 8) of integer range 0 to 7;
|
|
|
-- Most of the ALU instructions are the same as their Opcode equivalents with
|
-- Most of the ALU instructions are the same as their Opcode equivalents with
|
-- three exceptions (for IDLE, UPP2, and MUL2)
|
-- three exceptions (for IDLE, UPP2, and MUL2)
|
constant ALU_INC : OPCODE_TYPE := "00000"; -- x"00"
|
constant ALU_INC : OPCODE_TYPE := "00000"; -- x"00"
|
constant ALU_ADC : OPCODE_TYPE := "00001"; -- x"01"
|
constant ALU_ADC : OPCODE_TYPE := "00001"; -- x"01"
|
constant ALU_TX0 : OPCODE_TYPE := "00010"; -- x"02"
|
constant ALU_TX0 : OPCODE_TYPE := "00010"; -- x"02"
|
| Line 158... |
Line 268... |
end record;
|
end record;
|
|
|
constant ACCUM : SUBOP_TYPE := "000";
|
constant ACCUM : SUBOP_TYPE := "000";
|
constant INT_FLAG : SUBOP_TYPE := "011";
|
constant INT_FLAG : SUBOP_TYPE := "011";
|
|
|
-- There are only 8 byte-wide registers - and the write register is always 0,
|
|
-- so there is little point in making a RAM out of this
|
|
type REGFILE_TYPE is array (0 to 7) of DATA_TYPE;
|
type REGFILE_TYPE is array (0 to 7) of DATA_TYPE;
|
|
|
subtype FLAG_TYPE is DATA_TYPE;
|
subtype FLAG_TYPE is DATA_TYPE;
|
|
|
type PC_MODES is ( PC_IDLE, PC_REV1, PC_REV2, PC_INCR, PC_LOAD );
|
signal Halt : std_logic;
|
|
|
type PC_CTRL_TYPE is record
|
|
Oper : PC_MODES;
|
|
Offset : DATA_TYPE;
|
|
Addr : ADDRESS_TYPE;
|
|
end record;
|
|
|
|
type SP_MODES is ( SP_IDLE, SP_RSET, SP_POP, SP_PUSH );
|
|
|
|
type SP_CTRL_TYPE is record
|
|
Oper : SP_MODES;
|
|
Addr : ADDRESS_TYPE;
|
|
end record;
|
|
|
|
type INT_CTRL_TYPE is record
|
signal CPU_Next_State : CPU_STATES := PIPE_FILL_0;
|
Mask_Set : std_logic;
|
signal CPU_State : CPU_STATES := PIPE_FILL_0;
|
Mask_Data : DATA_TYPE;
|
|
Soft_Ints : INTERRUPT_BUNDLE;
|
|
Incr_ISR : std_logic;
|
|
end record;
|
|
|
|
type AS_MODES is ( ADDR_PC, ADDR_SP, ADDR_IMM, ADDR_ISR);
|
signal Cache_Ctrl : CACHE_MODES := CACHE_IDLE;
|
|
|
type ADDR_CTRL_TYPE is record
|
signal Opcode : OPCODE_TYPE := (others => '0');
|
Src : AS_MODES;
|
signal SubOp, SubOp_p1 : SUBOP_TYPE := (others => '0');
|
end record;
|
|
|
|
type DP_MODES is ( DATA_IDLE, DATA_REG, DATA_FLAG, DATA_PC );
|
signal Prefetch : DATA_TYPE := x"00";
|
|
signal Operand1, Operand2 : DATA_TYPE := x"00";
|
|
|
type DATA_CTRL_TYPE is record
|
signal Instr_Prefetch : std_logic := '0';
|
Src : DP_MODES;
|
|
Reg : SUBOP_TYPE;
|
|
end record;
|
|
|
|
signal Halt : std_logic;
|
|
signal ALU_Ctrl : ALU_CTRL_TYPE;
|
|
signal ALU_Regs : REGFILE_TYPE;
|
|
signal ALU_Flags : FLAG_TYPE;
|
|
signal PC_Ctrl : PC_CTRL_TYPE;
|
signal PC_Ctrl : PC_CTRL_TYPE;
|
|
signal Program_Ctr : ADDRESS_TYPE := x"0000";
|
|
|
signal SP_Ctrl : SP_CTRL_TYPE;
|
signal SP_Ctrl : SP_CTRL_TYPE;
|
signal AS_Ctrl : ADDR_CTRL_TYPE;
|
signal Stack_Ptr : ADDRESS_TYPE := x"0000";
|
|
|
signal DP_Ctrl : DATA_CTRL_TYPE;
|
signal DP_Ctrl : DATA_CTRL_TYPE;
|
|
|
signal INT_Ctrl : INT_CTRL_TYPE;
|
signal INT_Ctrl : INT_CTRL_TYPE;
|
signal Int_Req, Int_Ack : std_logic;
|
signal Ack_D, Ack_Q, Ack_Q1: std_logic := '0';
|
signal Int_RTI : std_logic;
|
signal Int_RTI_D, Int_RTI : std_logic := '0';
|
signal Int_Mask : DATA_TYPE;
|
signal Int_Req, Int_Ack : std_logic := '0';
|
signal PC : ADDRESS_TYPE;
|
signal Int_Mask : DATA_TYPE := x"00";
|
signal SP : ADDRESS_TYPE;
|
signal ISR_Addr : ADDRESS_TYPE := x"0000";
|
signal ISR : ADDRESS_TYPE;
|
signal i_Ints : INTERRUPT_BUNDLE := x"00";
|
signal IMM : ADDRESS_TYPE;
|
signal Pending : INTERRUPT_BUNDLE := x"00";
|
|
signal Wait_for_FSM : std_logic := '0';
|
|
signal History : INT_HIST := (others => 0);
|
|
signal Hst_Ptr : integer range 0 to 8 := 0;
|
|
|
|
signal ALU_Ctrl : ALU_CTRL_TYPE;
|
|
signal Regfile : REGFILE_TYPE;
|
|
signal Flags : FLAG_TYPE;
|
|
signal Mult : ADDRESS_TYPE := x"0000";
|
|
|
begin
|
begin
|
|
|
Halt_Disabled_fn: if( not Enable_CPU_Halt )generate
|
Halt_Disabled_fn: if( not Enable_CPU_Halt )generate
|
Halt <= '0';
|
Halt <= '0';
|
end generate;
|
end generate;
|
| Line 226... |
Line 323... |
Halt_Enabled_fn: if( Enable_CPU_Halt )generate
|
Halt_Enabled_fn: if( Enable_CPU_Halt )generate
|
Halt <= CPU_Halt;
|
Halt <= CPU_Halt;
|
end generate;
|
end generate;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- ALU (Arithmetic / Logic Unit)
|
-- State Logic / Instruction Decoding & Execution
|
-- Notes:
|
-- Combinatorial portion of CPU finite state machine
|
-- 1) Infers a multiplier in Xilinx/Altera parts - should be checked in others
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
Open8_ALU : block is
|
State_Logic: process(CPU_State, Regfile, Flags, Int_Mask, Opcode,
|
-- Preinitialization is for simulation only - check actual reset conditions
|
SubOp , SubOp_p1, Operand1, Operand2, Int_Req,
|
signal Regfile : REGFILE_TYPE := (others => (others => '0') );
|
Program_Ctr, Stack_Ptr, ISR_Addr )
|
signal Flags : FLAG_TYPE := (others => '0');
|
variable Reg, Reg_1 : integer range 0 to 7 := 0;
|
signal Mult : ADDRESS_TYPE := (others => '0');
|
variable Offset_SX : ADDRESS_TYPE;
|
begin
|
begin
|
|
CPU_Next_State <= CPU_State;
|
|
Cache_Ctrl <= CACHE_IDLE;
|
|
--
|
|
ALU_Ctrl.Oper <= ALU_IDLE;
|
|
ALU_Ctrl.Reg <= ACCUM;
|
|
ALU_Ctrl.Data <= x"00";
|
|
--
|
|
PC_Ctrl.Oper <= PC_IDLE;
|
|
PC_Ctrl.Offset <= x"03";
|
|
PC_Ctrl.Addr <= x"0000";
|
|
--
|
|
SP_Ctrl.Oper <= SP_IDLE;
|
|
--
|
|
Address <= Program_Ctr;
|
|
--
|
|
DP_Ctrl.Src <= DATA_IDLE;
|
|
DP_Ctrl.Reg <= ACCUM;
|
|
--
|
|
INT_Ctrl.Mask_Set <= '0';
|
|
INT_Ctrl.Soft_Ints <= x"00";
|
|
INT_Ctrl.Incr_ISR <= '0';
|
|
Ack_D <= '0';
|
|
Int_RTI_D <= '0';
|
|
|
ALU_Regs <= Regfile;
|
-- Assign the most common value of Reg and Reg1 outside the case structure
|
ALU_Flags <= Flags;
|
-- to simplify things.
|
|
Reg := conv_integer(SubOp);
|
|
Reg_1 := conv_integer(SubOp_p1);
|
|
Offset_SX(15 downto 0) := (others => Operand1(7));
|
|
Offset_SX(7 downto 0) := Operand1;
|
|
|
-- We need to infer a hardware multipler, so we create a special clocked
|
case CPU_State is
|
-- process with no reset or clock enable
|
-------------------------------------------------------------------------------
|
Multiplier: process( Clock )
|
-- Initial Instruction fetch & decode
|
begin
|
-------------------------------------------------------------------------------
|
if( rising_edge(Clock) )then
|
when PIPE_FILL_0 =>
|
Mult <= Regfile(0) *
|
CPU_Next_State <= PIPE_FILL_1;
|
Regfile(conv_integer(ALU_Ctrl.Reg));
|
PC_Ctrl.Oper <= PC_INCR;
|
end if;
|
|
end process;
|
|
|
|
ALU: process( Reset, Clock )
|
when PIPE_FILL_1 =>
|
variable Sum : std_logic_vector(8 downto 0) := "000000000";
|
CPU_Next_State <= PIPE_FILL_2;
|
variable Index : integer range 0 to 7 := 0;
|
PC_Ctrl.Oper <= PC_INCR;
|
variable Temp : std_logic_vector(8 downto 0);
|
|
begin
|
|
if( Reset = Reset_Level )then
|
|
for i in 0 to 7 loop
|
|
Regfile(i) <= (others => '0');
|
|
end loop;
|
|
Flags <= x"00";
|
|
elsif( rising_edge(Clock) )then
|
|
Temp := (others => '0');
|
|
Index := conv_integer(ALU_Ctrl.Reg);
|
|
if( Halt = '0' )then
|
|
case ALU_Ctrl.Oper is
|
|
when ALU_INC | ALU_UPP => -- Rn = Rn + 1 : Flags N,C,Z
|
|
Sum := ("0" & x"01") +
|
|
("0" & Regfile(Index));
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Regfile(Index) <= Sum(7 downto 0);
|
|
-- ALU_INC and ALU_UPP are essentially the same, except that ALU_UPP
|
|
-- doesn't set the N or Z flags. Note that the MSB can be used to
|
|
-- distinguish between the two ALU modes.
|
|
if( ALU_Ctrl.Oper(4) = '0' )then
|
|
Flags(FL_ZERO) <= '0';
|
|
if( Sum(7 downto 0) = 0 )then
|
|
Flags(FL_ZERO)<= '1';
|
|
end if;
|
|
Flags(FL_NEG) <= Sum(7);
|
|
end if;
|
|
|
|
when ALU_UPP2 => -- Rn = Rn + C
|
when PIPE_FILL_2 =>
|
Sum := ("0" & x"00") +
|
CPU_Next_State <= INSTR_DECODE;
|
("0" & Regfile(Index)) +
|
Cache_Ctrl <= CACHE_INSTR;
|
Flags(FL_CARRY);
|
PC_Ctrl.Oper <= PC_INCR;
|
Flags(FL_CARRY) <= Sum(8);
|
|
Regfile(Index) <= Sum(7 downto 0);
|
|
|
|
when ALU_ADC => -- R0 = R0 + Rn + C : Flags N,C,Z
|
when INSTR_DECODE =>
|
Sum := ("0" & Regfile(0)) +
|
CPU_Next_State <= INSTR_DECODE;
|
("0" & Regfile(Index)) +
|
Cache_Ctrl <= CACHE_INSTR;
|
Flags(FL_CARRY);
|
|
Flags(FL_ZERO) <= '0';
|
|
if( Sum(7 downto 0) = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
|
end if;
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Flags(FL_NEG) <= Sum(7);
|
|
Regfile(0) <= Sum(7 downto 0);
|
|
|
|
when ALU_TX0 => -- R0 = Rn : Flags N,Z
|
|
Temp := "0" & Regfile(Index);
|
|
Flags(FL_ZERO) <= '0';
|
|
if( Temp(7 downto 0) = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
|
end if;
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(0) <= Temp(7 downto 0);
|
|
|
|
when ALU_OR => -- R0 = R0 | Rn : Flags N,Z
|
|
Temp(7 downto 0) := Regfile(0) or Regfile(Index);
|
|
Flags(FL_ZERO) <= '0';
|
|
if( Temp(7 downto 0) = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
|
end if;
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(0) <= Temp(7 downto 0);
|
|
|
|
when ALU_AND => -- R0 = R0 & Rn : Flags N,Z
|
|
Temp(7 downto 0) := Regfile(0) and Regfile(Index);
|
|
Flags(FL_ZERO) <= '0';
|
|
if( Temp(7 downto 0) = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
|
end if;
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(0) <= Temp(7 downto 0);
|
|
|
|
when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z
|
|
Temp(7 downto 0) := Regfile(0) xor Regfile(Index);
|
|
Flags(FL_ZERO) <= '0';
|
|
if( Temp(7 downto 0) = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
|
end if;
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(0) <= Temp(7 downto 0);
|
|
|
|
when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z
|
|
Temp := Regfile(Index) & Flags(FL_CARRY);
|
|
Flags(FL_ZERO) <= '0';
|
|
if( Temp(7 downto 0) = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
|
end if;
|
|
Flags(FL_CARRY) <= Temp(8);
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(Index) <= Temp(7 downto 0);
|
|
|
|
when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z
|
|
Temp := Regfile(Index)(0) & Flags(FL_CARRY) &
|
|
Regfile(Index)(7 downto 1);
|
|
Flags(FL_ZERO) <= '0';
|
|
if( Temp(7 downto 0) = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
|
end if;
|
|
Flags(FL_CARRY) <= Temp(8);
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(Index) <= Temp(7 downto 0);
|
|
|
|
when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
|
|
Sum := ("0" & Regfile(Index)) +
|
|
("0" & x"FF");
|
|
Flags(FL_ZERO) <= '0';
|
|
if( Sum(7 downto 0) = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
|
end if;
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Flags(FL_NEG) <= Sum(7);
|
|
Regfile(Index) <= Sum(7 downto 0);
|
|
|
|
when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
|
|
Sum := ("0" & Regfile(0)) +
|
|
("0" & (not Regfile(Index))) +
|
|
Flags(FL_CARRY);
|
|
Flags(FL_ZERO) <= '0';
|
|
if( Sum(7 downto 0) = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
|
end if;
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Flags(FL_NEG) <= Sum(7);
|
|
Regfile(0) <= Sum(7 downto 0);
|
|
|
|
when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z
|
|
Sum := ("0" & Regfile(0)) +
|
|
("0" & Regfile(Index));
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Regfile(0) <= Sum(7 downto 0);
|
|
Flags(FL_ZERO) <= '0';
|
|
if( Sum(7 downto 0) = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
|
end if;
|
|
Flags(FL_NEG) <= Sum(7);
|
|
|
|
when ALU_STP => -- Sets bit(n) in the Flags register
|
|
Flags(Index) <= '1';
|
|
|
|
when ALU_BTT => -- Z = !R0(N), N = R0(7)
|
|
Flags(FL_ZERO) <= not Regfile(0)(Index);
|
|
Flags(FL_NEG) <= Regfile(0)(7);
|
|
|
|
when ALU_CLP => -- Clears bit(n) in the Flags register
|
|
Flags(Index) <= '0';
|
|
|
|
when ALU_T0X => -- Rn = R0 : Flags N,Z
|
|
Temp := "0" & Regfile(0);
|
|
Flags(FL_ZERO) <= '0';
|
|
if( Temp(7 downto 0) = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
|
end if;
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(Index) <= Temp(7 downto 0);
|
|
|
|
when ALU_CMP => -- Sets Flags on R0 - Rn : Flags N,C,Z
|
|
Sum := ("0" & Regfile(0)) +
|
|
("0" & (not Regfile(Index))) +
|
|
'1';
|
|
Flags(FL_ZERO) <= '0';
|
|
if( Sum(7 downto 0) = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
|
end if;
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Flags(FL_NEG) <= Sum(7);
|
|
|
|
when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
|
|
Regfile(0) <= Mult(7 downto 0);
|
|
Regfile(1) <= Mult(15 downto 8);
|
|
Flags(FL_ZERO) <= '0';
|
|
if( Mult = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
|
end if;
|
|
|
|
when ALU_LDI | ALU_POP => -- Rn <= Data : Flags N,Z
|
|
-- The POP instruction doesn't alter the flags, so we need to check
|
|
if( ALU_Ctrl.Oper = ALU_LDI )then
|
|
Flags(FL_ZERO) <= '0';
|
|
if( ALU_Ctrl.Data = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
|
end if;
|
|
Flags(FL_NEG) <= ALU_Ctrl.Data(7);
|
|
end if;
|
|
Regfile(Index) <= ALU_Ctrl.Data;
|
|
|
|
when ALU_LDX => -- R0 <= Data : Flags N,Z
|
|
Flags(FL_ZERO) <= '0';
|
|
if( ALU_Ctrl.Data = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
|
end if;
|
|
Flags(FL_NEG) <= ALU_Ctrl.Data(7);
|
|
Regfile(0) <= ALU_Ctrl.Data;
|
|
|
|
when ALU_RFLG =>
|
|
Flags <= ALU_Ctrl.Data;
|
|
|
|
when others => null;
|
|
end case;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
end block;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Program Counter
|
|
-------------------------------------------------------------------------------
|
|
|
|
Open8_PC : block is
|
|
-- Preinitialization is for simulation only - check actual reset conditions
|
|
signal PC_Q : ADDRESS_TYPE := (others => '0');
|
|
begin
|
|
|
|
PC <= PC_Q;
|
|
|
|
Program_Counter: process( Reset, Clock )
|
|
variable PC_Offset_SX : ADDRESS_TYPE := x"0000";
|
|
begin
|
|
if( Reset = Reset_Level )then
|
|
PC_Q <= Program_Start_Addr;
|
|
elsif( rising_edge(Clock) )then
|
|
PC_Offset_SX(15 downto 8):= (others => PC_Ctrl.Offset(7));
|
|
PC_Offset_SX(7 downto 0) := PC_Ctrl.Offset;
|
|
if( Halt = '0' )then
|
|
case PC_Ctrl.Oper is
|
|
when PC_IDLE =>
|
|
null;
|
|
when PC_REV1 =>
|
|
PC_Q <= PC_Q - 1;
|
|
when PC_REV2 =>
|
|
PC_Q <= PC_Q - 2;
|
|
when PC_INCR =>
|
|
PC_Q <= PC_Q + PC_Offset_SX - 2;
|
|
when PC_LOAD =>
|
|
PC_Q <= PC_Ctrl.Addr;
|
|
end case;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
end block;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Stack Pointer
|
|
-------------------------------------------------------------------------------
|
|
|
|
Open8_SP : block is
|
|
-- Preinitialization is for simulation only - check actual reset conditions
|
|
signal SP_Q : ADDRESS_TYPE := (others => '0');
|
|
begin
|
|
|
|
SP <= SP_Q;
|
|
|
|
Stack_Pointer: process( Reset, Clock )
|
|
begin
|
|
if( Reset = Reset_Level )then
|
|
SP_Q <= Stack_Start_Addr;
|
|
elsif( rising_edge(Clock) )then
|
|
if( Halt = '0' )then
|
|
case SP_Ctrl.Oper is
|
|
when SP_IDLE => null;
|
|
when SP_RSET => SP_Q <= SP_Ctrl.Addr;
|
|
when SP_POP => SP_Q <= SP_Q + 1;
|
|
when SP_PUSH => SP_Q <= SP_Q - 1;
|
|
end case;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
end block;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Address Source Mux
|
|
-------------------------------------------------------------------------------
|
|
|
|
Open8_AS : block is
|
|
begin
|
|
|
|
Address_Select: process( AS_Ctrl, PC, SP, IMM, ISR )
|
|
begin
|
|
Address <= (others => '0');
|
|
case AS_Ctrl.Src is
|
|
when ADDR_PC =>
|
|
Address <= PC;
|
|
when ADDR_SP =>
|
|
Address <= SP;
|
|
when ADDR_IMM =>
|
|
Address <= IMM;
|
|
when ADDR_ISR =>
|
|
Address <= ISR;
|
|
end case;
|
|
end process;
|
|
|
|
end block;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- (Write) Data Path
|
|
-------------------------------------------------------------------------------
|
|
|
|
Open8_DP : block is
|
|
begin
|
|
|
|
Data_Path: process( Reset, Clock )
|
|
begin
|
|
if( Reset = Reset_Level )then
|
|
Wr_Data <= (others => '0');
|
|
Wr_Enable <= '0';
|
|
Rd_Enable <= '1';
|
|
elsif( rising_edge(Clock) )then
|
|
if( Halt = '0' )then
|
|
Wr_Enable <= '0';
|
|
Rd_Enable <= '1';
|
|
case DP_Ctrl.Src is
|
|
when DATA_IDLE =>
|
|
null;
|
|
when DATA_REG =>
|
|
Wr_Enable <= '1';
|
|
Rd_Enable <= '0';
|
|
Wr_Data <= ALU_Regs(conv_integer(DP_Ctrl.Reg));
|
|
when DATA_FLAG =>
|
|
Wr_Enable <= '1';
|
|
Rd_Enable <= '0';
|
|
Wr_Data <= ALU_Flags;
|
|
when DATA_PC =>
|
|
Wr_Enable <= '1';
|
|
Rd_Enable <= '0';
|
|
Wr_Data <= PC(15 downto 8);
|
|
if( DP_Ctrl.Reg = ACCUM )then
|
|
Wr_Data <= PC(7 downto 0);
|
|
end if;
|
|
when others => null;
|
|
end case;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
end block;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Interrupt Controller
|
|
-------------------------------------------------------------------------------
|
|
|
|
Open8_INT : block is
|
|
|
|
-- Preinitialization is for simulation only - check actual reset conditions
|
|
constant INT_VECTOR_0 : ADDRESS_TYPE := ISR_Start_Addr;
|
|
constant INT_VECTOR_1 : ADDRESS_TYPE := ISR_Start_Addr+2;
|
|
constant INT_VECTOR_2 : ADDRESS_TYPE := ISR_Start_Addr+4;
|
|
constant INT_VECTOR_3 : ADDRESS_TYPE := ISR_Start_Addr+6;
|
|
constant INT_VECTOR_4 : ADDRESS_TYPE := ISR_Start_Addr+8;
|
|
constant INT_VECTOR_5 : ADDRESS_TYPE := ISR_Start_Addr+10;
|
|
constant INT_VECTOR_6 : ADDRESS_TYPE := ISR_Start_Addr+12;
|
|
constant INT_VECTOR_7 : ADDRESS_TYPE := ISR_Start_Addr+14;
|
|
|
|
signal i_Ints : INTERRUPT_BUNDLE := (others => '0');
|
|
signal Pending_D : INTERRUPT_BUNDLE := (others => '0');
|
|
signal Pending : INTERRUPT_BUNDLE := (others => '0');
|
|
signal Wait_for_FSM : std_logic := '0';
|
|
signal ISR_D, ISR_Q : ADDRESS_TYPE := (others => '0');
|
|
|
|
type INT_HIST is array (0 to 8) of integer range 0 to 7;
|
|
signal History : INT_HIST := (others => 0);
|
|
signal Int_Trig : std_logic := '0';
|
|
signal Hist_Level : integer range 0 to 7 := 0;
|
|
signal Hist_Ptr : integer range 0 to 8 := 0;
|
|
|
|
begin
|
|
|
|
ISR <= ISR_Q;
|
|
|
|
Int_Mask_proc: process( Int_Mask, Interrupts, INT_Ctrl )
|
|
variable S_Mask : std_logic_vector(7 downto 0);
|
|
begin
|
|
S_Mask := Int_Mask;
|
|
for i in 0 to 7 loop
|
|
i_Ints(i) <= (Interrupts(i) or INT_Ctrl.Soft_Ints(i))
|
|
and S_Mask(i);
|
|
end loop;
|
|
end process;
|
|
|
|
Int_Ctrl_proc: process( i_Ints, Pending, Wait_for_FSM, ISR_Q, INT_Ctrl,
|
|
History, Hist_Ptr )
|
|
begin
|
|
ISR_D <= ISR_Q;
|
|
Pending_D <= Pending;
|
|
Int_Trig <= '0';
|
|
Hist_Level <= 0;
|
|
|
|
-- Record any incoming interrupts to the pending buffer
|
|
if( i_Ints > 0 )then
|
|
Pending_D <= i_Ints;
|
|
end if;
|
|
|
|
-- Incr_ISR allows the CPU Core to advance the vector address to pop the
|
|
-- lower half of the address.
|
|
if( INT_Ctrl.Incr_ISR = '1' )then
|
|
ISR_D <= ISR_Q + 1;
|
|
end if;
|
|
|
|
-- Only mess with interrupt signals while the CPU core is not currently
|
|
-- working with the ISR address (ie, not loading a new service vector)
|
|
if( Wait_for_FSM = '0' and Pending > 0 )then
|
|
if( Pending(0) = '1' and (Hist_Ptr = 0 or History(Hist_Ptr) > 0) )then
|
|
ISR_D <= INT_VECTOR_0;
|
|
Pending_D(0) <= '0';
|
|
Hist_Level <= 0;
|
|
Int_Trig <= '1';
|
|
elsif( Pending(1) = '1' and (Hist_Ptr = 0 or History(Hist_Ptr) > 1) )then
|
|
ISR_D <= INT_VECTOR_1;
|
|
Pending_D(1) <= '0';
|
|
Hist_Level <= 1;
|
|
Int_Trig <= '1';
|
|
elsif( Pending(2) = '1' and (Hist_Ptr = 0 or History(Hist_Ptr) > 2) )then
|
|
ISR_D <= INT_VECTOR_2;
|
|
Pending_D(2) <= '0';
|
|
Hist_Level <= 2;
|
|
Int_Trig <= '1';
|
|
elsif( Pending(3) = '1' and (Hist_Ptr = 0 or History(Hist_Ptr) > 3) )then
|
|
ISR_D <= INT_VECTOR_3;
|
|
Pending_D(3) <= '0';
|
|
Hist_Level <= 3;
|
|
Int_Trig <= '1';
|
|
elsif( Pending(4) = '1' and (Hist_Ptr = 0 or History(Hist_Ptr) > 4) )then
|
|
ISR_D <= INT_VECTOR_4;
|
|
Pending_D(4) <= '0';
|
|
Hist_Level <= 4;
|
|
Int_Trig <= '1';
|
|
elsif( Pending(5) = '1' and (Hist_Ptr = 0 or History(Hist_Ptr) > 5) )then
|
|
ISR_D <= INT_VECTOR_5;
|
|
Pending_D(5) <= '0';
|
|
Hist_Level <= 5;
|
|
Int_Trig <= '1';
|
|
elsif( Pending(6) = '1' and (Hist_Ptr = 0 or History(Hist_Ptr) > 6) )then
|
|
ISR_D <= INT_VECTOR_6;
|
|
Pending_D(6) <= '0';
|
|
Hist_Level <= 6;
|
|
Int_Trig <= '1';
|
|
elsif( Pending(7) = '1' and (Hist_Ptr = 0 or History(Hist_Ptr) > 7) )then
|
|
ISR_D <= INT_VECTOR_7;
|
|
Pending_D(7) <= '0';
|
|
Hist_Level <= 7;
|
|
Int_Trig <= '1';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
S_Regs: process( Reset, Clock )
|
|
begin
|
|
if( Reset = Reset_Level )then
|
|
Int_Req <= '0';
|
|
Pending <= x"00";
|
|
Wait_for_FSM <= '0';
|
|
Int_Mask <= Default_Interrupt_Mask(7 downto 1) & '1';
|
|
ISR_Q <= INT_VECTOR_0;
|
|
for i in 0 to 8 loop
|
|
History(i) <= 0;
|
|
end loop;
|
|
Hist_Ptr <= 0;
|
|
elsif( rising_edge(Clock) )then
|
|
if( Halt = '0' )then
|
|
Int_Req <= Wait_for_FSM and (not Int_Ack);
|
|
Pending <= Pending_D;
|
|
-- Reset the Wait_for_FSM flag on Int_Ack
|
|
if( Int_Ack = '1' )then
|
|
Wait_for_FSM <= '0';
|
|
-- Set the Wait_for_FSM flag on Int_Trig
|
|
elsif( Int_Trig = '1' )then
|
|
Wait_for_FSM <= '1';
|
|
end if;
|
|
if( INT_Ctrl.Mask_Set = '1' )then
|
|
Int_Mask <= INT_Ctrl.Mask_Data(7 downto 1) & '1';
|
|
end if;
|
|
ISR_Q <= ISR_D;
|
|
if( Int_Trig = '1' )then
|
|
History(Hist_Ptr+1) <= Hist_Level;
|
|
Hist_Ptr <= Hist_Ptr + 1;
|
|
elsif( Int_RTI = '1' and Hist_Ptr > 0 )then
|
|
Hist_Ptr <= Hist_Ptr - 1;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
end block;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- State Logic / Instruction Decoding & Execution
|
|
-------------------------------------------------------------------------------
|
|
|
|
Open8_FSM : block is
|
|
|
|
-- These are all the primary instructions/op-codes (upper 5-bits)
|
|
constant OP_INC : OPCODE_TYPE := "00000";
|
|
constant OP_ADC : OPCODE_TYPE := "00001";
|
|
constant OP_TX0 : OPCODE_TYPE := "00010";
|
|
constant OP_OR : OPCODE_TYPE := "00011";
|
|
constant OP_AND : OPCODE_TYPE := "00100";
|
|
constant OP_XOR : OPCODE_TYPE := "00101";
|
|
constant OP_ROL : OPCODE_TYPE := "00110";
|
|
constant OP_ROR : OPCODE_TYPE := "00111";
|
|
constant OP_DEC : OPCODE_TYPE := "01000";
|
|
constant OP_SBC : OPCODE_TYPE := "01001";
|
|
constant OP_ADD : OPCODE_TYPE := "01010";
|
|
constant OP_STP : OPCODE_TYPE := "01011";
|
|
constant OP_BTT : OPCODE_TYPE := "01100";
|
|
constant OP_CLP : OPCODE_TYPE := "01101";
|
|
constant OP_T0X : OPCODE_TYPE := "01110";
|
|
constant OP_CMP : OPCODE_TYPE := "01111";
|
|
constant OP_PSH : OPCODE_TYPE := "10000";
|
|
constant OP_POP : OPCODE_TYPE := "10001";
|
|
constant OP_BR0 : OPCODE_TYPE := "10010";
|
|
constant OP_BR1 : OPCODE_TYPE := "10011";
|
|
constant OP_DBNZ : OPCODE_TYPE := "10100"; -- USR
|
|
constant OP_INT : OPCODE_TYPE := "10101";
|
|
constant OP_MUL : OPCODE_TYPE := "10110"; -- USR2
|
|
constant OP_STK : OPCODE_TYPE := "10111";
|
|
constant OP_UPP : OPCODE_TYPE := "11000";
|
|
constant OP_STA : OPCODE_TYPE := "11001";
|
|
constant OP_STX : OPCODE_TYPE := "11010";
|
|
constant OP_STO : OPCODE_TYPE := "11011";
|
|
constant OP_LDI : OPCODE_TYPE := "11100";
|
|
constant OP_LDA : OPCODE_TYPE := "11101";
|
|
constant OP_LDX : OPCODE_TYPE := "11110";
|
|
constant OP_LDO : OPCODE_TYPE := "11111";
|
|
|
|
-- These are all specific sub-opcodes for OP_STK / 0xB8 (lower 3-bits)
|
|
constant SOP_RSP : SUBOP_TYPE := "000";
|
|
constant SOP_RTS : SUBOP_TYPE := "001";
|
|
constant SOP_RTI : SUBOP_TYPE := "010";
|
|
constant SOP_BRK : SUBOP_TYPE := "011";
|
|
constant SOP_JMP : SUBOP_TYPE := "100";
|
|
constant SOP_SMSK : SUBOP_TYPE := "101";
|
|
constant SOP_GMSK : SUBOP_TYPE := "110";
|
|
constant SOP_JSR : SUBOP_TYPE := "111";
|
|
|
|
-- Preinitialization is for simulation only - check actual reset conditions
|
|
type CPU_STATES is (
|
|
-- Instruction fetch & Decode
|
|
PIPE_FILL_0, PIPE_FILL_1, PIPE_FILL_2, INSTR_DECODE,
|
|
-- Branching
|
|
BRN_C1, DBNZ_C1, JMP_C1, JMP_C2,
|
|
-- Loads
|
|
LDA_C1, LDA_C2, LDA_C3, LDA_C4, LDI_C1, LDO_C1, LDX_C1, LDX_C2, LDX_C3,
|
|
-- Stores
|
|
STA_C1, STA_C2, STA_C3, STO_C1, STO_C2, STX_C1, STX_C2,
|
|
-- 2-cycle math
|
|
MUL_C1, UPP_C1,
|
|
-- Stack
|
|
PSH_C1, POP_C1, POP_C2, POP_C3, POP_C4,
|
|
-- Subroutines & Interrupts
|
|
WAIT_FOR_INT, ISR_C1, ISR_C2, ISR_C3, JSR_C1, JSR_C2,
|
|
RTS_C1, RTS_C2, RTS_C3, RTS_C4, RTS_C5, RTI_C6,
|
|
-- Debugging
|
|
BRK_C1 );
|
|
|
|
signal CPU_Next_State : CPU_STATES := PIPE_FILL_0;
|
|
signal CPU_State : CPU_STATES := PIPE_FILL_0;
|
|
|
|
type CACHE_MODES is (CACHE_IDLE, CACHE_INSTR, CACHE_OPER1, CACHE_OPER2,
|
|
CACHE_PREFETCH );
|
|
signal Cache_Ctrl : CACHE_MODES := CACHE_IDLE;
|
|
|
|
signal Opcode : OPCODE_TYPE := (others => '0');
|
|
signal SubOp, SubOp_p1 : SUBOP_TYPE := (others => '0');
|
|
-- synthesis translate_off
|
|
signal Instruction : DATA_TYPE := (others => '0');
|
|
-- synthesis translate_on
|
|
signal Prefetch : DATA_TYPE := (others => '0');
|
|
signal Operand1, Operand2 : DATA_TYPE := (others => '0');
|
|
|
|
signal Instr_Prefetch : std_logic := '0';
|
|
|
|
signal Ack_D, Ack_Q, Ack_Q1: std_logic := '0';
|
|
signal Int_RTI_D : std_logic := '0';
|
|
|
|
begin
|
|
|
|
-- synthesis translate_off
|
|
Instruction <= Opcode & SubOp;
|
|
-- synthesis translate_on
|
|
|
|
State_Logic: process(CPU_State, ALU_Regs, ALU_Flags, Int_Mask, Opcode,
|
|
SubOp , SubOp_p1, Operand1, Operand2, Int_Req )
|
|
variable Reg, Reg_1 : integer range 0 to 7 := 0;
|
|
variable Offset_SX : ADDRESS_TYPE;
|
|
begin
|
|
CPU_Next_State <= CPU_State;
|
|
Cache_Ctrl <= CACHE_IDLE;
|
|
--
|
|
ALU_Ctrl.Oper <= ALU_IDLE;
|
|
ALU_Ctrl.Reg <= ACCUM;
|
|
ALU_Ctrl.Data <= x"00";
|
|
--
|
|
PC_Ctrl.Oper <= PC_IDLE;
|
|
|
|
PC_Ctrl.Offset <= x"03";
|
|
PC_Ctrl.Addr <= x"0000";
|
|
--
|
|
SP_Ctrl.Oper <= SP_IDLE;
|
|
--
|
|
AS_Ctrl.Src <= ADDR_PC;
|
|
IMM <= x"0000";
|
|
--
|
|
DP_Ctrl.Src <= DATA_IDLE;
|
|
DP_Ctrl.Reg <= ACCUM;
|
|
--
|
|
INT_Ctrl.Mask_Set <= '0';
|
|
INT_Ctrl.Soft_Ints <= x"00";
|
|
INT_Ctrl.Incr_ISR <= '0';
|
|
Ack_D <= '0';
|
|
Int_RTI_D <= '0';
|
|
|
|
-- Assign the most common value of Reg and Reg1 outside the case structure
|
|
-- to simplify things.
|
|
Reg := conv_integer(SubOp);
|
|
Reg_1 := conv_integer(SubOp_p1);
|
|
Offset_SX(15 downto 0) := (others => Operand1(7));
|
|
Offset_SX(7 downto 0) := Operand1;
|
|
|
|
case CPU_State is
|
|
-------------------------------------------------------------------------------
|
|
-- Initial Instruction fetch & decode
|
|
-------------------------------------------------------------------------------
|
|
when PIPE_FILL_0 =>
|
|
CPU_Next_State <= PIPE_FILL_1;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
|
when PIPE_FILL_1 =>
|
|
CPU_Next_State <= PIPE_FILL_2;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
|
when PIPE_FILL_2 =>
|
|
CPU_Next_State <= INSTR_DECODE;
|
|
Cache_Ctrl <= CACHE_INSTR;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
|
when INSTR_DECODE =>
|
|
CPU_Next_State <= INSTR_DECODE;
|
|
Cache_Ctrl <= CACHE_INSTR;
|
|
|
|
case Opcode is
|
case Opcode is
|
when OP_PSH =>
|
when OP_PSH =>
|
CPU_Next_State <= PSH_C1;
|
CPU_Next_State <= PSH_C1;
|
Cache_Ctrl <= CACHE_PREFETCH;
|
Cache_Ctrl <= CACHE_PREFETCH;
|
| Line 1006... |
Line 495... |
PC_Ctrl.Oper <= PC_REV2;
|
PC_Ctrl.Oper <= PC_REV2;
|
|
|
when OP_LDX =>
|
when OP_LDX =>
|
CPU_Next_State <= LDX_C1;
|
CPU_Next_State <= LDX_C1;
|
PC_Ctrl.Oper <= PC_REV2;
|
PC_Ctrl.Oper <= PC_REV2;
|
AS_Ctrl.Src <= ADDR_IMM;
|
|
-- If auto-increment is disabled, use the specified register pair,
|
-- If auto-increment is disabled, use the specified register pair,
|
-- otherwise, for an odd:even pair, and issue the first half of
|
-- otherwise, for an odd:even pair, and issue the first half of
|
-- a UPP instruction to the ALU
|
-- a UPP instruction to the ALU
|
if( not Enable_Auto_Increment )then
|
if( not Enable_Auto_Increment )then
|
IMM <= ALU_Regs(Reg_1) & ALU_Regs(Reg);
|
Address <= Regfile(Reg_1) & Regfile(Reg);
|
|
else
|
|
Reg := conv_integer(SubOp(2 downto 1) & '0');
|
|
Reg_1 := conv_integer(SubOp(2 downto 1) & '1');
|
|
Address <= Regfile(Reg_1) & Regfile(Reg);
|
|
if( SubOp(0) = '1' )then
|
|
ALU_Ctrl.Oper<= ALU_UPP;
|
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
|
end if;
|
|
end if;
|
|
|
|
when OP_STA =>
|
|
CPU_Next_State <= STA_C1;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
|
|
|
when OP_STO =>
|
|
CPU_Next_State <= STO_C1;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
|
PC_Ctrl.Oper <= PC_REV2;
|
|
DP_Ctrl.Src <= DATA_REG;
|
|
DP_Ctrl.Reg <= ACCUM;
|
|
|
|
when OP_STX =>
|
|
CPU_Next_State <= STX_C1;
|
|
Cache_Ctrl <= CACHE_PREFETCH;
|
|
PC_Ctrl.Oper <= PC_REV2;
|
|
DP_Ctrl.Src <= DATA_REG;
|
|
DP_Ctrl.Reg <= ACCUM;
|
|
|
|
when others =>
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= Opcode;
|
|
ALU_Ctrl.Reg <= SubOp;
|
|
|
|
end case;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Program Control (BR0_C1, BR1_C1, DBNZ_C1, JMP )
|
|
-------------------------------------------------------------------------------
|
|
|
|
when BRN_C1 =>
|
|
CPU_Next_State <= INSTR_DECODE;
|
|
Cache_Ctrl <= CACHE_INSTR;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
if( Flags(Reg) = Opcode(0) )then
|
|
CPU_Next_State <= PIPE_FILL_0;
|
|
Cache_Ctrl <= CACHE_IDLE;
|
|
PC_Ctrl.Offset <= Operand1;
|
|
end if;
|
|
|
|
when DBNZ_C1 =>
|
|
CPU_Next_State <= INSTR_DECODE;
|
|
Cache_Ctrl <= CACHE_INSTR;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
if( Flags(FL_ZERO) = '0' )then
|
|
CPU_Next_State <= PIPE_FILL_0;
|
|
Cache_Ctrl <= CACHE_IDLE;
|
|
PC_Ctrl.Offset <= Operand1;
|
|
end if;
|
|
|
|
when JMP_C1 =>
|
|
CPU_Next_State <= JMP_C2;
|
|
Cache_Ctrl <= CACHE_OPER2;
|
|
|
|
when JMP_C2 =>
|
|
CPU_Next_State <= PIPE_FILL_0;
|
|
PC_Ctrl.Oper <= PC_LOAD;
|
|
PC_Ctrl.Addr <= Operand2 & Operand1;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Data Storage - Load from memory (LDA, LDI, LDO, LDX)
|
|
-------------------------------------------------------------------------------
|
|
|
|
when LDA_C1 =>
|
|
CPU_Next_State <= LDA_C2;
|
|
Cache_Ctrl <= CACHE_OPER2;
|
|
|
|
when LDA_C2 =>
|
|
CPU_Next_State <= LDA_C3;
|
|
Address <= Operand2 & Operand1;
|
|
|
|
when LDA_C3 =>
|
|
CPU_Next_State <= LDA_C4;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
|
when LDA_C4 =>
|
|
CPU_Next_State <= LDI_C1;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
|
when LDI_C1 =>
|
|
CPU_Next_State <= INSTR_DECODE;
|
|
Cache_Ctrl <= CACHE_INSTR;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= ALU_LDI;
|
|
ALU_Ctrl.Reg <= SubOp;
|
|
ALU_Ctrl.Data <= Operand1;
|
|
|
|
when LDO_C1 =>
|
|
CPU_Next_State <= LDX_C1;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
if( Enable_Auto_Increment )then
|
|
Reg := conv_integer(SubOp(2 downto 1) & '0');
|
|
Reg_1 := conv_integer(SubOp(2 downto 1) & '1');
|
|
Address <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
|
|
if( SubOp(0) = '1' )then
|
|
ALU_Ctrl.Oper<= ALU_UPP;
|
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
|
end if;
|
|
else
|
|
Address <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
|
|
end if;
|
|
|
|
when LDX_C1 =>
|
|
CPU_Next_State <= LDX_C2;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
|
when LDX_C2 =>
|
|
CPU_Next_State <= LDX_C3;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
|
|
|
when LDX_C3 =>
|
|
CPU_Next_State <= INSTR_DECODE;
|
|
Cache_Ctrl <= CACHE_INSTR;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= ALU_LDX;
|
|
ALU_Ctrl.Reg <= ACCUM;
|
|
ALU_Ctrl.Data <= Operand1;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Data Storage - Store to memory (STA, STO, STX)
|
|
-------------------------------------------------------------------------------
|
|
when STA_C1 =>
|
|
CPU_Next_State <= STA_C2;
|
|
Cache_Ctrl <= CACHE_OPER2;
|
|
DP_Ctrl.Src <= DATA_REG;
|
|
DP_Ctrl.Reg <= SubOp;
|
|
|
|
when STA_C2 =>
|
|
CPU_Next_State <= STA_C3;
|
|
Address <= Operand2 & Operand1;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
|
when STA_C3 =>
|
|
CPU_Next_State <= PIPE_FILL_2;
|
|
Cache_Ctrl <= CACHE_PREFETCH;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
|
when STO_C1 =>
|
|
Cache_Ctrl <= CACHE_PREFETCH;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
-- If auto-increment is disabled, just load the registers normally
|
|
if( not Enable_Auto_Increment )then
|
|
CPU_Next_State <= PIPE_FILL_1;
|
|
Address <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
|
|
-- Otherwise, enforce the even register rule, and check the LSB to see
|
|
-- if we should perform the auto-increment on the register pair
|
|
else
|
|
CPU_Next_State <= PIPE_FILL_0;
|
|
Reg := conv_integer(SubOp(2 downto 1) & '0');
|
|
Reg_1 := conv_integer(SubOp(2 downto 1) & '1');
|
|
Address <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
|
|
if( SubOp(0) = '1' )then
|
|
CPU_Next_State <= STO_C2;
|
|
ALU_Ctrl.Oper <= ALU_UPP;
|
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
|
end if;
|
|
end if;
|
|
|
|
when STO_C2 =>
|
|
CPU_Next_State <= PIPE_FILL_1;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= ALU_UPP2;
|
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '1';
|
|
|
|
when STX_C1 =>
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
-- If auto-increment is disabled, just load the registers normally
|
|
if( not Enable_Auto_Increment )then
|
|
CPU_Next_State <= PIPE_FILL_1;
|
|
Address <= (Regfile(Reg_1) & Regfile(Reg));
|
|
-- Otherwise, enforce the even register rule, and check the LSB to see
|
|
-- if we should perform the auto-increment on the register pair
|
else
|
else
|
|
CPU_Next_State <= PIPE_FILL_1;
|
Reg := conv_integer(SubOp(2 downto 1) & '0');
|
Reg := conv_integer(SubOp(2 downto 1) & '0');
|
Reg_1 := conv_integer(SubOp(2 downto 1) & '1');
|
Reg_1 := conv_integer(SubOp(2 downto 1) & '1');
|
IMM <= ALU_Regs(Reg_1) & ALU_Regs(Reg);
|
Address <= (Regfile(Reg_1) & Regfile(Reg));
|
if( SubOp(0) = '1' )then
|
if( SubOp(0) = '1' )then
|
|
CPU_Next_State <= STX_C2;
|
ALU_Ctrl.Oper<= ALU_UPP;
|
ALU_Ctrl.Oper<= ALU_UPP;
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when OP_STA =>
|
when STX_C2 =>
|
CPU_Next_State <= STA_C1;
|
CPU_Next_State <= PIPE_FILL_2;
|
Cache_Ctrl <= CACHE_OPER1;
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= ALU_UPP2;
|
when OP_STO =>
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '1';
|
CPU_Next_State <= STO_C1;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
|
PC_Ctrl.Oper <= PC_REV2;
|
|
DP_Ctrl.Src <= DATA_REG;
|
|
DP_Ctrl.Reg <= ACCUM;
|
|
|
|
when OP_STX =>
|
-------------------------------------------------------------------------------
|
CPU_Next_State <= STX_C1;
|
-- Multi-Cycle Math Operations (UPP, MUL)
|
Cache_Ctrl <= CACHE_PREFETCH;
|
-------------------------------------------------------------------------------
|
PC_Ctrl.Oper <= PC_REV2;
|
-- Because we have to backup the pipeline by 1 to refetch the 2nd
|
DP_Ctrl.Src <= DATA_REG;
|
-- instruction/first operand, we have to return through PF2
|
DP_Ctrl.Reg <= ACCUM;
|
|
|
|
when others =>
|
when MUL_C1 =>
|
|
CPU_Next_State <= PIPE_FILL_2;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Oper <= PC_INCR;
|
ALU_Ctrl.Oper <= Opcode;
|
ALU_Ctrl.Oper <= ALU_MUL;
|
ALU_Ctrl.Reg <= SubOp;
|
|
|
|
end case;
|
when UPP_C1 =>
|
|
CPU_Next_State <= PIPE_FILL_2;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= ALU_UPP2;
|
|
ALU_Ctrl.Reg <= SubOp_p1;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Program Control (BR0_C1, BR1_C1, DBNZ_C1, JMP )
|
-- Basic Stack Manipulation (PSH, POP, RSP)
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
when PSH_C1 =>
|
|
CPU_Next_State <= PIPE_FILL_1;
|
|
Address <= Stack_Ptr;
|
|
SP_Ctrl.Oper <= SP_PUSH;
|
|
|
when BRN_C1 =>
|
when POP_C1 =>
|
CPU_Next_State <= INSTR_DECODE;
|
CPU_Next_State <= POP_C2;
|
Cache_Ctrl <= CACHE_INSTR;
|
Address <= Stack_Ptr;
|
|
|
|
when POP_C2 =>
|
|
CPU_Next_State <= POP_C3;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Oper <= PC_INCR;
|
if( ALU_Flags(Reg) = Opcode(0) )then
|
|
CPU_Next_State <= PIPE_FILL_0;
|
|
Cache_Ctrl <= CACHE_IDLE;
|
|
PC_Ctrl.Offset <= Operand1;
|
|
end if;
|
|
|
|
when DBNZ_C1 =>
|
when POP_C3 =>
|
|
CPU_Next_State <= POP_C4;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
|
when POP_C4 =>
|
CPU_Next_State <= INSTR_DECODE;
|
CPU_Next_State <= INSTR_DECODE;
|
Cache_Ctrl <= CACHE_INSTR;
|
Cache_Ctrl <= CACHE_INSTR;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Oper <= PC_INCR;
|
if( ALU_Flags(FL_ZERO) = '0' )then
|
ALU_Ctrl.Oper <= ALU_POP;
|
|
ALU_Ctrl.Reg <= SubOp;
|
|
ALU_Ctrl.Data <= Operand1;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Subroutines & Interrupts (RTS, JSR)
|
|
-------------------------------------------------------------------------------
|
|
when WAIT_FOR_INT => -- For soft interrupts only, halt the Program_Ctr
|
|
CPU_Next_State <= WAIT_FOR_INT;
|
|
|
|
when ISR_C1 =>
|
|
CPU_Next_State <= ISR_C2;
|
|
Address <= ISR_Addr;
|
|
INT_Ctrl.Incr_ISR <= '1';
|
|
|
|
when ISR_C2 =>
|
|
CPU_Next_State <= ISR_C3;
|
|
Address <= ISR_Addr;
|
|
DP_Ctrl.Src <= DATA_FLAG;
|
|
|
|
when ISR_C3 =>
|
|
CPU_Next_State <= JSR_C1;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
|
Address <= Stack_Ptr;
|
|
SP_Ctrl.Oper <= SP_PUSH;
|
|
DP_Ctrl.Src <= DATA_PC;
|
|
DP_Ctrl.Reg <= ACCUM+1;
|
|
ALU_Ctrl.Oper <= ALU_STP;
|
|
ALU_Ctrl.Reg <= INT_FLAG;
|
|
Ack_D <= '1';
|
|
|
|
when JSR_C1 =>
|
|
CPU_Next_State <= JSR_C2;
|
|
Cache_Ctrl <= CACHE_OPER2;
|
|
Address <= Stack_Ptr;
|
|
SP_Ctrl.Oper <= SP_PUSH;
|
|
DP_Ctrl.Src <= DATA_PC;
|
|
DP_Ctrl.Reg <= ACCUM;
|
|
|
|
when JSR_C2 =>
|
CPU_Next_State <= PIPE_FILL_0;
|
CPU_Next_State <= PIPE_FILL_0;
|
Cache_Ctrl <= CACHE_IDLE;
|
Address <= Stack_Ptr;
|
PC_Ctrl.Offset <= Operand1;
|
SP_Ctrl.Oper <= SP_PUSH;
|
|
PC_Ctrl.Oper <= PC_LOAD;
|
|
PC_Ctrl.Addr <= Operand2 & Operand1;
|
|
|
|
when RTS_C1 =>
|
|
CPU_Next_State <= RTS_C2;
|
|
Address <= Stack_Ptr;
|
|
SP_Ctrl.Oper <= SP_POP;
|
|
|
|
when RTS_C2 =>
|
|
CPU_Next_State <= RTS_C3;
|
|
Address <= Stack_Ptr;
|
|
-- if this is an RTI, then we need to POP the flags
|
|
if( SubOp = SOP_RTI )then
|
|
SP_Ctrl.Oper <= SP_POP;
|
end if;
|
end if;
|
|
|
when JMP_C1 =>
|
when RTS_C3 =>
|
CPU_Next_State <= JMP_C2;
|
CPU_Next_State <= RTS_C4;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
|
-- It doesn't really matter what is on the address bus for RTS, while
|
|
-- it does for RTI, so we make this the default
|
|
Address <= Stack_Ptr;
|
|
|
|
when RTS_C4 =>
|
|
CPU_Next_State <= RTS_C5;
|
Cache_Ctrl <= CACHE_OPER2;
|
Cache_Ctrl <= CACHE_OPER2;
|
|
|
when JMP_C2 =>
|
when RTS_C5 =>
|
CPU_Next_State <= PIPE_FILL_0;
|
CPU_Next_State <= PIPE_FILL_0;
|
PC_Ctrl.Oper <= PC_LOAD;
|
PC_Ctrl.Oper <= PC_LOAD;
|
PC_Ctrl.Addr <= Operand2 & Operand1;
|
PC_Ctrl.Addr <= Operand2 & Operand1;
|
|
if( SubOp = SOP_RTI )then
|
|
CPU_Next_State <= RTI_C6;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
|
end if;
|
|
|
|
when RTI_C6 =>
|
|
CPU_Next_State <= PIPE_FILL_1;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= ALU_RFLG;
|
|
ALU_Ctrl.Data <= Operand1;
|
|
Int_RTI_D <= '1';
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Data Storage - Load from memory (LDA, LDI, LDO, LDX)
|
-- Debugging (BRK) Performs a 5-clock NOP
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
when BRK_C1 =>
|
|
CPU_Next_State <= PIPE_FILL_0;
|
|
|
when LDA_C1 =>
|
when others =>
|
CPU_Next_State <= LDA_C2;
|
null;
|
Cache_Ctrl <= CACHE_OPER2;
|
end case;
|
|
|
when LDA_C2 =>
|
|
CPU_Next_State <= LDA_C3;
|
|
AS_Ctrl.Src <= ADDR_IMM;
|
|
IMM <= Operand2 & Operand1;
|
|
|
|
when LDA_C3 =>
|
-- Interrupt service routines can only begin during the decode and wait
|
CPU_Next_State <= LDA_C4;
|
-- states to avoid corruption due to incomplete instruction execution
|
|
if( Int_Req = '1' )then
|
|
if( CPU_State = INSTR_DECODE or CPU_State = WAIT_FOR_INT )then
|
|
-- Reset all of the sub-block controls to IDLE, to avoid unintended
|
|
-- operation due to the current instruction
|
|
ALU_Ctrl.Oper <= ALU_IDLE;
|
|
Cache_Ctrl <= CACHE_IDLE;
|
|
SP_Ctrl.Oper <= SP_IDLE;
|
|
DP_Ctrl.Src <= DATA_IDLE; -- JSH 7/20
|
|
INT_Ctrl.Soft_Ints <= (others => '0'); -- JSH 7/22
|
|
-- Rewind the PC by 3 to compensate for the pipeline registers
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Oper <= PC_INCR;
|
|
PC_Ctrl.Offset <= x"FF";
|
|
CPU_Next_State <= ISR_C1;
|
|
|
|
end if;
|
|
end if;
|
|
|
|
end process;
|
|
|
|
-- We need to infer a hardware multipler, so we create a special clocked
|
|
-- process with no reset or clock enable
|
|
Multiplier_proc: process( Clock )
|
|
begin
|
|
if( rising_edge(Clock) )then
|
|
Mult <= Regfile(0) *
|
|
Regfile(conv_integer(ALU_Ctrl.Reg));
|
|
end if;
|
|
end process;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Registered portion of CPU finite state machine
|
|
-------------------------------------------------------------------------------
|
|
CPU_Regs: process( Reset, Clock )
|
|
variable Offset_SX : ADDRESS_TYPE;
|
|
variable i_Ints : INTERRUPT_BUNDLE := (others => '0');
|
|
variable Sum : std_logic_vector(8 downto 0) := "000000000";
|
|
variable Index : integer range 0 to 7 := 0;
|
|
variable Temp : std_logic_vector(8 downto 0);
|
|
begin
|
|
if( Reset = Reset_Level )then
|
|
CPU_State <= PIPE_FILL_0;
|
|
Opcode <= OP_INC;
|
|
SubOp <= ACCUM;
|
|
SubOp_p1 <= ACCUM;
|
|
Operand1 <= x"00";
|
|
Operand2 <= x"00";
|
|
Instr_Prefetch <= '0';
|
|
Prefetch <= x"00";
|
|
|
|
Wr_Data <= (others => '0');
|
|
Wr_Enable <= '0';
|
|
Rd_Enable <= '1';
|
|
|
|
Program_Ctr <= Program_Start_Addr;
|
|
Stack_Ptr <= Stack_Start_Addr;
|
|
|
|
Ack_Q <= '0';
|
|
Ack_Q1 <= '0';
|
|
Int_Ack <= '0';
|
|
Int_RTI <= '0';
|
|
|
|
Int_Req <= '0';
|
|
Pending <= x"00";
|
|
Wait_for_FSM <= '0';
|
|
Int_Mask <= Default_Interrupt_Mask(7 downto 1) & '1';
|
|
ISR_Addr <= INT_VECTOR_0;
|
|
for i in 0 to 8 loop
|
|
History(i) <= 0;
|
|
end loop;
|
|
Hst_Ptr <= 0;
|
|
|
|
for i in 0 to 7 loop
|
|
Regfile(i) <= (others => '0');
|
|
end loop;
|
|
Flags <= x"00";
|
|
|
|
elsif( rising_edge(Clock) )then
|
|
Wr_Enable <= '0';
|
|
Rd_Enable <= '0';
|
|
|
|
if( Halt = '0' )then
|
|
Rd_Enable <= '1';
|
|
-------------------------------------------------------------------------------
|
|
-- Instruction/Operand caching for pipelined memory access
|
|
-------------------------------------------------------------------------------
|
|
CPU_State <= CPU_Next_State;
|
|
case Cache_Ctrl is
|
|
when CACHE_INSTR =>
|
|
Opcode <= Rd_Data(7 downto 3);
|
|
SubOp <= Rd_Data(2 downto 0);
|
|
SubOp_p1 <= Rd_Data(2 downto 0) + 1;
|
|
if( Instr_Prefetch = '1' )then
|
|
Opcode <= Prefetch(7 downto 3);
|
|
SubOp <= Prefetch(2 downto 0);
|
|
SubOp_p1 <= Prefetch(2 downto 0) + 1;
|
|
Instr_Prefetch <= '0';
|
|
end if;
|
|
|
|
when CACHE_OPER1 =>
|
|
Operand1 <= Rd_Data;
|
|
|
|
when CACHE_OPER2 =>
|
|
Operand2 <= Rd_Data;
|
|
|
|
when CACHE_PREFETCH =>
|
|
Prefetch <= Rd_Data;
|
|
Instr_Prefetch <= '1';
|
|
|
|
when CACHE_IDLE =>
|
|
null;
|
|
end case;
|
|
|
when LDA_C4 =>
|
-------------------------------------------------------------------------------
|
CPU_Next_State <= LDI_C1;
|
-- Program Counter
|
Cache_Ctrl <= CACHE_OPER1;
|
-------------------------------------------------------------------------------
|
PC_Ctrl.Oper <= PC_INCR;
|
Offset_SX(15 downto 8) := (others => PC_Ctrl.Offset(7));
|
|
Offset_SX(7 downto 0) := PC_Ctrl.Offset;
|
|
|
when LDI_C1 =>
|
case PC_Ctrl.Oper is
|
CPU_Next_State <= INSTR_DECODE;
|
when PC_IDLE =>
|
Cache_Ctrl <= CACHE_INSTR;
|
null;
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= ALU_LDI;
|
|
ALU_Ctrl.Reg <= SubOp;
|
|
ALU_Ctrl.Data <= Operand1;
|
|
|
|
when LDO_C1 =>
|
when PC_REV1 =>
|
CPU_Next_State <= LDX_C1;
|
Program_Ctr <= Program_Ctr - 1;
|
AS_Ctrl.Src <= ADDR_IMM;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
if( Enable_Auto_Increment )then
|
|
Reg := conv_integer(SubOp(2 downto 1) & '0');
|
|
Reg_1 := conv_integer(SubOp(2 downto 1) & '1');
|
|
IMM <= (ALU_Regs(Reg_1) & ALU_Regs(Reg)) + Offset_SX;
|
|
if( SubOp(0) = '1' )then
|
|
ALU_Ctrl.Oper<= ALU_UPP;
|
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
|
end if;
|
|
else
|
|
IMM <= (ALU_Regs(Reg_1) & ALU_Regs(Reg)) + Offset_SX;
|
|
end if;
|
|
|
|
when LDX_C1 =>
|
when PC_REV2 =>
|
CPU_Next_State <= LDX_C2;
|
Program_Ctr <= Program_Ctr - 2;
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
|
when LDX_C2 =>
|
when PC_INCR =>
|
CPU_Next_State <= LDX_C3;
|
Program_Ctr <= Program_Ctr + Offset_SX - 2;
|
PC_Ctrl.Oper <= PC_INCR;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
|
|
|
when LDX_C3 =>
|
when PC_LOAD =>
|
CPU_Next_State <= INSTR_DECODE;
|
Program_Ctr <= PC_Ctrl.Addr;
|
Cache_Ctrl <= CACHE_INSTR;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
when others =>
|
ALU_Ctrl.Oper <= ALU_LDX;
|
null;
|
ALU_Ctrl.Reg <= ACCUM;
|
end case;
|
ALU_Ctrl.Data <= Operand1;
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Data Storage - Store to memory (STA, STO, STX)
|
-- (Write) Data Path
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
when STA_C1 =>
|
case DP_Ctrl.Src is
|
CPU_Next_State <= STA_C2;
|
when DATA_IDLE =>
|
Cache_Ctrl <= CACHE_OPER2;
|
null;
|
DP_Ctrl.Src <= DATA_REG;
|
|
DP_Ctrl.Reg <= SubOp;
|
|
|
|
when STA_C2 =>
|
when DATA_REG =>
|
CPU_Next_State <= STA_C3;
|
Wr_Enable <= '1';
|
AS_Ctrl.Src <= ADDR_IMM;
|
Rd_Enable <= '0';
|
IMM <= Operand2 & Operand1;
|
Wr_Data <= Regfile(conv_integer(DP_Ctrl.Reg));
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
|
when STA_C3 =>
|
when DATA_FLAG =>
|
CPU_Next_State <= PIPE_FILL_2;
|
Wr_Enable <= '1';
|
Cache_Ctrl <= CACHE_PREFETCH;
|
Rd_Enable <= '0';
|
PC_Ctrl.Oper <= PC_INCR;
|
Wr_Data <= Flags;
|
|
|
when STO_C1 =>
|
when DATA_PC =>
|
Cache_Ctrl <= CACHE_PREFETCH;
|
Wr_Enable <= '1';
|
PC_Ctrl.Oper <= PC_INCR;
|
Rd_Enable <= '0';
|
AS_Ctrl.Src <= ADDR_IMM;
|
Wr_Data <= Program_Ctr(15 downto 8);
|
-- If auto-increment is disabled, just load the registers normally
|
if( DP_Ctrl.Reg = ACCUM )then
|
if( not Enable_Auto_Increment )then
|
Wr_Data <= Program_Ctr(7 downto 0);
|
CPU_Next_State <= PIPE_FILL_1;
|
|
IMM <= (ALU_Regs(Reg_1) & ALU_Regs(Reg)) + Offset_SX;
|
|
-- Otherwise, enforce the even register rule, and check the LSB to see
|
|
-- if we should perform the auto-increment on the register pair
|
|
else
|
|
CPU_Next_State <= PIPE_FILL_0;
|
|
Reg := conv_integer(SubOp(2 downto 1) & '0');
|
|
Reg_1 := conv_integer(SubOp(2 downto 1) & '1');
|
|
IMM <= (ALU_Regs(Reg_1) & ALU_Regs(Reg)) + Offset_SX;
|
|
if( SubOp(0) = '1' )then
|
|
CPU_Next_State <= STO_C2;
|
|
ALU_Ctrl.Oper <= ALU_UPP;
|
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
|
end if;
|
|
end if;
|
end if;
|
|
|
when STO_C2 =>
|
when others =>
|
CPU_Next_State <= PIPE_FILL_1;
|
null;
|
PC_Ctrl.Oper <= PC_INCR;
|
end case;
|
ALU_Ctrl.Oper <= ALU_UPP2;
|
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '1';
|
|
|
|
when STX_C1 =>
|
-------------------------------------------------------------------------------
|
PC_Ctrl.Oper <= PC_INCR;
|
-- Stack Pointer
|
AS_Ctrl.Src <= ADDR_IMM;
|
-------------------------------------------------------------------------------
|
-- If auto-increment is disabled, just load the registers normally
|
case SP_Ctrl.Oper is
|
if( not Enable_Auto_Increment )then
|
when SP_IDLE =>
|
CPU_Next_State <= PIPE_FILL_1;
|
null;
|
IMM <= (ALU_Regs(Reg_1) & ALU_Regs(Reg));
|
|
-- Otherwise, enforce the even register rule, and check the LSB to see
|
when SP_RSET =>
|
-- if we should perform the auto-increment on the register pair
|
-- The original RSP instruction simply reset the stack pointer to the preset
|
else
|
-- address set at compile time. However, with little extra effort, we can
|
CPU_Next_State <= PIPE_FILL_1;
|
-- modify the instruction to allow the stack pointer to be moved anywhere in
|
Reg := conv_integer(SubOp(2 downto 1) & '0');
|
-- the memory map. Since RSP can't have an sub-opcode, R1:R0 was chosen as
|
Reg_1 := conv_integer(SubOp(2 downto 1) & '1');
|
-- a fixed source
|
IMM <= (ALU_Regs(Reg_1) & ALU_Regs(Reg));
|
Stack_Ptr <= Stack_Start_Addr;
|
if( SubOp(0) = '1' )then
|
if( Allow_Stack_Address_Move )then
|
CPU_Next_State <= STX_C2;
|
Stack_Ptr <= Regfile(1) & Regfile(0);
|
ALU_Ctrl.Oper <= ALU_UPP;
|
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
|
end if;
|
|
end if;
|
end if;
|
|
|
when STX_C2 =>
|
when SP_POP =>
|
CPU_Next_State <= PIPE_FILL_2;
|
Stack_Ptr <= Stack_Ptr + 1;
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= ALU_UPP2;
|
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '1';
|
|
|
|
-------------------------------------------------------------------------------
|
when SP_PUSH =>
|
-- Multi-Cycle Math Operations (UPP, MUL)
|
Stack_Ptr <= Stack_Ptr - 1;
|
-------------------------------------------------------------------------------
|
|
-- Because we have to backup the pipeline by 1 to refetch the 2nd
|
|
-- instruction/first operand, we have to return through PF2
|
|
|
|
when MUL_C1 =>
|
when others =>
|
CPU_Next_State <= PIPE_FILL_2;
|
null;
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= ALU_MUL;
|
|
|
|
when UPP_C1 =>
|
end case;
|
CPU_Next_State <= PIPE_FILL_2;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= ALU_UPP2;
|
|
ALU_Ctrl.Reg <= SubOp_p1;
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Basic Stack Manipulation (PSH, POP, RSP)
|
-- Interrupt Controller
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
when PSH_C1 =>
|
-- The interrupt control mask is always sourced out of R0
|
CPU_Next_State <= PIPE_FILL_1;
|
if( INT_Ctrl.Mask_Set = '1' )then
|
AS_Ctrl.Src <= ADDR_SP;
|
Int_Mask <= Regfile(conv_integer(ACCUM))(7 downto 1) & '1';
|
SP_Ctrl.Oper <= SP_PUSH;
|
end if;
|
|
|
when POP_C1 =>
|
-- Combine external and internal interrupts, and mask the OR or the two
|
CPU_Next_State <= POP_C2;
|
-- with the mask. Record any incoming interrupts to the pending buffer
|
AS_Ctrl.Src <= ADDR_SP;
|
i_Ints := (Interrupts or INT_Ctrl.Soft_Ints) and
|
|
Int_Mask;
|
|
if( i_Ints > 0 )then
|
|
Pending <= i_Ints;
|
|
end if;
|
|
|
when POP_C2 =>
|
-- Only mess with interrupt signals while the CPU core is not currently
|
CPU_Next_State <= POP_C3;
|
-- working with, or loading, an ISR address
|
PC_Ctrl.Oper <= PC_INCR;
|
if( Wait_for_FSM = '0' and Pending > 0 )then
|
|
if( Pending(0) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 0))then
|
|
ISR_Addr <= INT_VECTOR_0;
|
|
Pending(0) <= '0';
|
|
History(Hst_Ptr+1) <= 0;
|
|
Hst_Ptr <= Hst_Ptr + 1;
|
|
Wait_for_FSM <= '1';
|
|
elsif(Pending(1) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 1))then
|
|
ISR_Addr <= INT_VECTOR_1;
|
|
Pending(1) <= '0';
|
|
History(Hst_Ptr+1) <= 1;
|
|
Hst_Ptr <= Hst_Ptr + 1;
|
|
Wait_for_FSM <= '1';
|
|
elsif(Pending(2) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 2))then
|
|
ISR_Addr <= INT_VECTOR_2;
|
|
Pending(2) <= '0';
|
|
History(Hst_Ptr+1) <= 1;
|
|
Hst_Ptr <= Hst_Ptr + 1;
|
|
Wait_for_FSM <= '1';
|
|
elsif(Pending(3) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 3))then
|
|
ISR_Addr <= INT_VECTOR_3;
|
|
Pending(3) <= '0';
|
|
History(Hst_Ptr+1) <= 3;
|
|
Hst_Ptr <= Hst_Ptr + 1;
|
|
Wait_for_FSM <= '1';
|
|
elsif(Pending(4) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 4))then
|
|
ISR_Addr <= INT_VECTOR_4;
|
|
Pending(4) <= '0';
|
|
History(Hst_Ptr+1) <= 4;
|
|
Hst_Ptr <= Hst_Ptr + 1;
|
|
Wait_for_FSM <= '1';
|
|
elsif(Pending(5) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 5))then
|
|
ISR_Addr <= INT_VECTOR_5;
|
|
Pending(5) <= '0';
|
|
History(Hst_Ptr+1) <= 5;
|
|
Hst_Ptr <= Hst_Ptr + 1;
|
|
Wait_for_FSM <= '1';
|
|
elsif(Pending(6) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 6))then
|
|
ISR_Addr <= INT_VECTOR_6;
|
|
Pending(6) <= '0';
|
|
History(Hst_Ptr+1) <= 6;
|
|
Hst_Ptr <= Hst_Ptr + 1;
|
|
Wait_for_FSM <= '1';
|
|
elsif(Pending(7) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 7))then
|
|
ISR_Addr <= INT_VECTOR_7;
|
|
Pending(7) <= '0';
|
|
History(Hst_Ptr+1) <= 7;
|
|
Hst_Ptr <= Hst_Ptr + 1;
|
|
Wait_for_FSM <= '1';
|
|
end if;
|
|
end if;
|
|
|
when POP_C3 =>
|
-- Reset the Wait_for_FSM flag on Int_Ack
|
CPU_Next_State <= POP_C4;
|
Ack_Q <= Ack_D;
|
Cache_Ctrl <= CACHE_OPER1;
|
Ack_Q1 <= Ack_Q;
|
PC_Ctrl.Oper <= PC_INCR;
|
Int_Ack <= Ack_Q1;
|
|
if( Int_Ack = '1' )then
|
|
Wait_for_FSM <= '0';
|
|
end if;
|
|
|
when POP_C4 =>
|
Int_Req <= Wait_for_FSM and (not Int_Ack);
|
CPU_Next_State <= INSTR_DECODE;
|
|
Cache_Ctrl <= CACHE_INSTR;
|
Int_RTI <= Int_RTI_D;
|
PC_Ctrl.Oper <= PC_INCR;
|
if( Int_RTI = '1' and Hst_Ptr > 0 )then
|
ALU_Ctrl.Oper <= ALU_POP;
|
Hst_Ptr <= Hst_Ptr - 1;
|
ALU_Ctrl.Reg <= SubOp;
|
end if;
|
ALU_Ctrl.Data <= Operand1;
|
|
|
-- Incr_ISR allows the CPU Core to advance the vector address to pop the
|
|
-- lower half of the address.
|
|
if( INT_Ctrl.Incr_ISR = '1' )then
|
|
ISR_Addr <= ISR_Addr + 1;
|
|
end if;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Subroutines & Interrupts (RTS, JSR)
|
-- ALU (Arithmetic / Logic Unit)
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
when WAIT_FOR_INT => -- For soft interrupts only, halt the PC
|
Temp := (others => '0');
|
CPU_Next_State <= WAIT_FOR_INT;
|
Index := conv_integer(ALU_Ctrl.Reg);
|
|
|
when ISR_C1 =>
|
case ALU_Ctrl.Oper is
|
CPU_Next_State <= ISR_C2;
|
when ALU_INC | ALU_UPP => -- Rn = Rn + 1 : Flags N,C,Z
|
AS_Ctrl.Src <= ADDR_ISR;
|
Sum := ("0" & x"01") +
|
INT_Ctrl.Incr_ISR <= '1';
|
("0" & Regfile(Index));
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Regfile(Index) <= Sum(7 downto 0);
|
|
-- ALU_INC and ALU_UPP are essentially the same, except that ALU_UPP
|
|
-- doesn't set the N or Z flags. Note that the MSB can be used to
|
|
-- distinguish between the two ALU modes.
|
|
if( ALU_Ctrl.Oper(4) = '0' )then
|
|
Flags(FL_ZERO) <= '0';
|
|
if( Sum(7 downto 0) = 0 )then
|
|
Flags(FL_ZERO)<= '1';
|
|
end if;
|
|
Flags(FL_NEG) <= Sum(7);
|
|
end if;
|
|
|
when ISR_C2 =>
|
when ALU_UPP2 => -- Rn = Rn + C
|
CPU_Next_State <= ISR_C3;
|
Sum := ("0" & x"00") +
|
AS_Ctrl.Src <= ADDR_ISR;
|
("0" & Regfile(Index)) +
|
DP_Ctrl.Src <= DATA_FLAG;
|
Flags(FL_CARRY);
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Regfile(Index) <= Sum(7 downto 0);
|
|
|
|
when ALU_ADC => -- R0 = R0 + Rn + C : Flags N,C,Z
|
|
Sum := ("0" & Regfile(0)) +
|
|
("0" & Regfile(Index)) +
|
|
Flags(FL_CARRY);
|
|
Flags(FL_ZERO) <= '0';
|
|
if( Sum(7 downto 0) = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
|
end if;
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Flags(FL_NEG) <= Sum(7);
|
|
Regfile(0) <= Sum(7 downto 0);
|
|
|
|
when ALU_TX0 => -- R0 = Rn : Flags N,Z
|
|
Temp := "0" & Regfile(Index);
|
|
Flags(FL_ZERO) <= '0';
|
|
if( Temp(7 downto 0) = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
|
end if;
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(0) <= Temp(7 downto 0);
|
|
|
when ISR_C3 =>
|
when ALU_OR => -- R0 = R0 | Rn : Flags N,Z
|
CPU_Next_State <= JSR_C1;
|
Temp(7 downto 0) := Regfile(0) or Regfile(Index);
|
Cache_Ctrl <= CACHE_OPER1;
|
Flags(FL_ZERO) <= '0';
|
AS_Ctrl.Src <= ADDR_SP;
|
if( Temp(7 downto 0) = 0 )then
|
SP_Ctrl.Oper <= SP_PUSH;
|
Flags(FL_ZERO) <= '1';
|
DP_Ctrl.Src <= DATA_PC;
|
end if;
|
DP_Ctrl.Reg <= ACCUM+1;
|
Flags(FL_NEG) <= Temp(7);
|
ALU_Ctrl.Oper <= ALU_STP;
|
Regfile(0) <= Temp(7 downto 0);
|
ALU_Ctrl.Reg <= INT_FLAG;
|
|
Ack_D <= '1';
|
|
|
|
when JSR_C1 =>
|
when ALU_AND => -- R0 = R0 & Rn : Flags N,Z
|
CPU_Next_State <= JSR_C2;
|
Temp(7 downto 0) := Regfile(0) and Regfile(Index);
|
Cache_Ctrl <= CACHE_OPER2;
|
Flags(FL_ZERO) <= '0';
|
AS_Ctrl.Src <= ADDR_SP;
|
if( Temp(7 downto 0) = 0 )then
|
SP_Ctrl.Oper <= SP_PUSH;
|
Flags(FL_ZERO) <= '1';
|
DP_Ctrl.Src <= DATA_PC;
|
end if;
|
DP_Ctrl.Reg <= ACCUM;
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(0) <= Temp(7 downto 0);
|
|
|
when JSR_C2 =>
|
when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z
|
CPU_Next_State <= PIPE_FILL_0;
|
Temp(7 downto 0) := Regfile(0) xor Regfile(Index);
|
AS_Ctrl.Src <= ADDR_SP;
|
Flags(FL_ZERO) <= '0';
|
SP_Ctrl.Oper <= SP_PUSH;
|
if( Temp(7 downto 0) = 0 )then
|
PC_Ctrl.Oper <= PC_LOAD;
|
Flags(FL_ZERO) <= '1';
|
PC_Ctrl.Addr <= Operand2 & Operand1;
|
end if;
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(0) <= Temp(7 downto 0);
|
|
|
when RTS_C1 =>
|
when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z
|
CPU_Next_State <= RTS_C2;
|
Temp := Regfile(Index) & Flags(FL_CARRY);
|
AS_Ctrl.Src <= ADDR_SP;
|
Flags(FL_ZERO) <= '0';
|
SP_Ctrl.Oper <= SP_POP;
|
if( Temp(7 downto 0) = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
|
end if;
|
|
Flags(FL_CARRY) <= Temp(8);
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(Index) <= Temp(7 downto 0);
|
|
|
when RTS_C2 =>
|
when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z
|
CPU_Next_State <= RTS_C3;
|
Temp := Regfile(Index)(0) & Flags(FL_CARRY) &
|
AS_Ctrl.Src <= ADDR_SP;
|
Regfile(Index)(7 downto 1);
|
-- if this is an RTI, then we need to POP the flags
|
Flags(FL_ZERO) <= '0';
|
if( SubOp = SOP_RTI )then
|
if( Temp(7 downto 0) = 0 )then
|
SP_Ctrl.Oper <= SP_POP;
|
Flags(FL_ZERO) <= '1';
|
end if;
|
end if;
|
|
Flags(FL_CARRY) <= Temp(8);
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(Index) <= Temp(7 downto 0);
|
|
|
when RTS_C3 =>
|
when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
|
CPU_Next_State <= RTS_C4;
|
Sum := ("0" & Regfile(Index)) +
|
Cache_Ctrl <= CACHE_OPER1;
|
("0" & x"FF");
|
-- It doesn't really matter what is on the address bus for RTS, while
|
Flags(FL_ZERO) <= '0';
|
-- it does for RTI, so we make this the default
|
if( Sum(7 downto 0) = 0 )then
|
AS_Ctrl.Src <= ADDR_SP;
|
Flags(FL_ZERO) <= '1';
|
|
end if;
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Flags(FL_NEG) <= Sum(7);
|
|
Regfile(Index) <= Sum(7 downto 0);
|
|
|
when RTS_C4 =>
|
when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
|
CPU_Next_State <= RTS_C5;
|
Sum := ("0" & Regfile(0)) +
|
Cache_Ctrl <= CACHE_OPER2;
|
("0" & (not Regfile(Index))) +
|
|
Flags(FL_CARRY);
|
|
Flags(FL_ZERO) <= '0';
|
|
if( Sum(7 downto 0) = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
|
end if;
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Flags(FL_NEG) <= Sum(7);
|
|
Regfile(0) <= Sum(7 downto 0);
|
|
|
when RTS_C5 =>
|
when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z
|
CPU_Next_State <= PIPE_FILL_0;
|
Sum := ("0" & Regfile(0)) +
|
PC_Ctrl.Oper <= PC_LOAD;
|
("0" & Regfile(Index));
|
PC_Ctrl.Addr <= Operand2 & Operand1;
|
Flags(FL_CARRY) <= Sum(8);
|
if( SubOp = SOP_RTI )then
|
Regfile(0) <= Sum(7 downto 0);
|
CPU_Next_State <= RTI_C6;
|
Flags(FL_ZERO) <= '0';
|
Cache_Ctrl <= CACHE_OPER1;
|
if( Sum(7 downto 0) = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
end if;
|
end if;
|
|
Flags(FL_NEG) <= Sum(7);
|
|
|
when RTI_C6 =>
|
when ALU_STP => -- Sets bit(n) in the Flags register
|
CPU_Next_State <= PIPE_FILL_1;
|
Flags(Index) <= '1';
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= ALU_RFLG;
|
|
ALU_Ctrl.Data <= Operand1;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
Int_RTI_D <= '1';
|
|
|
|
-------------------------------------------------------------------------------
|
when ALU_BTT => -- Z = !R0(N), N = R0(7)
|
-- Debugging (BRK) Performs a 5-clock NOP
|
Flags(FL_ZERO) <= not Regfile(0)(Index);
|
-------------------------------------------------------------------------------
|
Flags(FL_NEG) <= Regfile(0)(7);
|
when BRK_C1 =>
|
|
CPU_Next_State <= PIPE_FILL_0;
|
|
|
|
when others => null;
|
when ALU_CLP => -- Clears bit(n) in the Flags register
|
end case;
|
Flags(Index) <= '0';
|
|
|
-- Interrupt service routines can only begin during the decode and wait
|
when ALU_T0X => -- Rn = R0 : Flags N,Z
|
-- states to avoid corruption due to incomplete instruction execution
|
Temp := "0" & Regfile(0);
|
if( Int_Req = '1' )then
|
Flags(FL_ZERO) <= '0';
|
if( CPU_State = INSTR_DECODE or CPU_State = WAIT_FOR_INT )then
|
if( Temp(7 downto 0) = 0 )then
|
-- Reset all of the sub-block controls to IDLE, to avoid unintended
|
Flags(FL_ZERO) <= '1';
|
-- operation due to the current instruction
|
end if;
|
ALU_Ctrl.Oper <= ALU_IDLE;
|
Flags(FL_NEG) <= Temp(7);
|
Cache_Ctrl <= CACHE_IDLE;
|
Regfile(Index) <= Temp(7 downto 0);
|
SP_Ctrl.Oper <= SP_IDLE;
|
|
DP_Ctrl.Src <= DATA_IDLE; -- JSH 7/20
|
|
INT_Ctrl.Soft_Ints <= (others => '0'); -- JSH 7/22
|
|
-- Rewind the PC by 3 to compensate for the pipeline registers
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
PC_Ctrl.Offset <= x"FF";
|
|
CPU_Next_State <= ISR_C1;
|
|
|
|
|
when ALU_CMP => -- Sets Flags on R0 - Rn : Flags N,C,Z
|
|
Sum := ("0" & Regfile(0)) +
|
|
("0" & (not Regfile(Index))) +
|
|
'1';
|
|
Flags(FL_ZERO) <= '0';
|
|
if( Sum(7 downto 0) = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
end if;
|
end if;
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Flags(FL_NEG) <= Sum(7);
|
|
|
|
when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
|
|
Regfile(0) <= Mult(7 downto 0);
|
|
Regfile(1) <= Mult(15 downto 8);
|
|
Flags(FL_ZERO) <= '0';
|
|
if( Mult = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
end if;
|
end if;
|
|
|
end process;
|
when ALU_LDI | ALU_POP => -- Rn <= Data : Flags N,Z
|
|
-- The POP instruction doesn't alter the flags, so we need to check
|
|
if( ALU_Ctrl.Oper = ALU_LDI )then
|
|
Flags(FL_ZERO) <= '0';
|
|
if( ALU_Ctrl.Data = 0 )then
|
|
Flags(FL_ZERO) <= '1';
|
|
end if;
|
|
Flags(FL_NEG) <= ALU_Ctrl.Data(7);
|
|
end if;
|
|
Regfile(Index) <= ALU_Ctrl.Data;
|
|
|
S_Regs: process( Reset, Clock )
|
when ALU_LDX => -- R0 <= Data : Flags N,Z
|
begin
|
Flags(FL_ZERO) <= '0';
|
if( Reset = Reset_Level )then
|
if( ALU_Ctrl.Data = 0 )then
|
CPU_State <= PIPE_FILL_0;
|
Flags(FL_ZERO) <= '1';
|
Opcode <= OP_INC;
|
end if;
|
SubOp <= ACCUM;
|
Flags(FL_NEG) <= ALU_Ctrl.Data(7);
|
SubOp_p1 <= ACCUM;
|
Regfile(0) <= ALU_Ctrl.Data;
|
Operand1 <= x"00";
|
|
Operand2 <= x"00";
|
|
Instr_Prefetch <= '0';
|
|
Prefetch <= x"00";
|
|
|
|
Ack_Q <= '0';
|
when ALU_RFLG =>
|
Ack_Q1 <= '0';
|
Flags <= ALU_Ctrl.Data;
|
Int_Ack <= '0';
|
|
Int_RTI <= '0';
|
|
|
|
elsif( rising_edge(Clock) )then
|
when others =>
|
if( Halt = '0' )then
|
|
CPU_State <= CPU_Next_State;
|
|
case Cache_Ctrl is
|
|
when CACHE_INSTR =>
|
|
Opcode <= Rd_Data(7 downto 3);
|
|
SubOp <= Rd_Data(2 downto 0);
|
|
SubOp_p1 <= Rd_Data(2 downto 0) + 1;
|
|
if( Instr_Prefetch = '1' )then
|
|
Opcode <= Prefetch(7 downto 3);
|
|
SubOp <= Prefetch(2 downto 0);
|
|
SubOp_p1 <= Prefetch(2 downto 0) + 1;
|
|
Instr_Prefetch <= '0';
|
|
end if;
|
|
when CACHE_OPER1 =>
|
|
Operand1 <= Rd_Data;
|
|
when CACHE_OPER2 =>
|
|
Operand2 <= Rd_Data;
|
|
when CACHE_PREFETCH =>
|
|
Prefetch <= Rd_Data;
|
|
Instr_Prefetch <= '1';
|
|
when CACHE_IDLE =>
|
|
null;
|
null;
|
end case;
|
end case;
|
|
|
-- Interrupt signalling registers
|
|
Ack_Q <= Ack_D;
|
|
Ack_Q1 <= Ack_Q;
|
|
Int_Ack <= Ack_Q1;
|
|
Int_RTI <= Int_RTI_D;
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-------------------------------------------------------------------------------
|
end architecture;
|
-- Fixed in-line statements for the interrupt mask, and stack pointer address
|
|
-------------------------------------------------------------------------------
|
|
|
|
-- The interrupt control mask is always sourced out of R0
|
|
INT_Ctrl.Mask_Data <= ALU_Regs(conv_integer(ACCUM));
|
|
|
|
-- The original RSP instruction simply reset the stack pointer to the preset
|
|
-- address set at compile time. However, with little extra effort, we can
|
|
-- modify the instruction to allow the stack pointer to be moved anywhere in
|
|
-- the memory map. Since RSP can't have an sub-opcode, R1:R0 was chosen as
|
|
-- a fixed source
|
|
|
|
Prog_Stack_Addr_Move_fn: if( Allow_Stack_Address_Move )generate
|
|
SP_Ctrl.Addr <= ALU_Regs(1) & ALU_Regs(0);
|
|
end generate;
|
|
|
|
Normal_Stack_Reset_fn: if( not Allow_Stack_Address_Move )generate
|
|
SP_Ctrl.Addr <= Stack_Start_Addr;
|
|
end generate;
|
|
|
|
end block;
|
|
|
|
end rtl;
|
|
|
|
No newline at end of file
|
No newline at end of file
|
