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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_cpu.vhd] - Diff between revs 156 and 162

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Rev 156 Rev 162
Line 74... Line 74...
------------------ -------- ---------------------------------------------------
------------------ -------- ---------------------------------------------------
-- Seth Henry      07/19/06 Design Start
-- Seth Henry      07/19/06 Design Start
-- Seth Henry      01/18/11 Fixed BTT instruction to match V8
-- Seth Henry      01/18/11 Fixed BTT instruction to match V8
-- Seth Henry      07/22/11 Fixed interrupt transition logic to avoid data
-- Seth Henry      07/22/11 Fixed interrupt transition logic to avoid data
--                           corruption issues.
--                           corruption issues.
-- Seth Henry      07/26/11 Optimized logic in ALU, stack pointer, and data path
-- Seth Henry      07/26/11 Optimized logic in ALU, stack pointer, and data
--                           sections.
--                           path sections.
-- Seth Henry      07/27/11 Optimized logic for timing, merged blocks into
-- Seth Henry      07/27/11 Optimized logic for timing, merged blocks into
--                           single entity.
--                           single entity.
 
-- Seth Henry      09/20/11 Added BRK_Implements_WAI option, allowing the
 
--                           processor to wait for an interrupt instead of the
 
--                           normal BRK behavior.
 
 
library ieee;
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_arith.all;
Line 91... Line 94...
 
 
entity Open8_CPU is
entity Open8_CPU is
  generic(
  generic(
    Stack_Start_Addr         : ADDRESS_TYPE := x"007F"; -- Top of Stack
    Stack_Start_Addr         : ADDRESS_TYPE := x"007F"; -- Top of Stack
    Allow_Stack_Address_Move : boolean      := false;   -- Use Normal v8 RSP
    Allow_Stack_Address_Move : boolean      := false;   -- Use Normal v8 RSP
 
    BRK_Implements_WAI       : boolean      := false;   -- BRK -> Wait for Int
    ISR_Start_Addr           : ADDRESS_TYPE := x"0080"; -- Bottom of ISR vec's
    ISR_Start_Addr           : ADDRESS_TYPE := x"0080"; -- Bottom of ISR vec's
    Program_Start_Addr       : ADDRESS_TYPE := x"0090"; -- Initial PC location
    Program_Start_Addr       : ADDRESS_TYPE := x"0090"; -- Initial PC location
    Default_Interrupt_Mask   : DATA_TYPE    := x"FF";   -- Enable all Ints
    Default_Interrupt_Mask   : DATA_TYPE    := x"FF";   -- Enable all Ints
    Enable_CPU_Halt          : boolean      := false;   -- Disable HALT pin
    Enable_CPU_Halt          : boolean      := false;   -- Disable HALT pin
    Enable_Auto_Increment    : boolean      := false;   -- Modify indexed instr
    Enable_Auto_Increment    : boolean      := false;   -- Modify indexed instr
Line 432... Line 436...
                SP_Ctrl.Oper <= SP_POP;
                SP_Ctrl.Oper <= SP_POP;
 
 
              when SOP_BRK  =>
              when SOP_BRK  =>
                CPU_Next_State <= BRK_C1;
                CPU_Next_State <= BRK_C1;
                PC_Ctrl.Oper <= PC_REV2;
                PC_Ctrl.Oper <= PC_REV2;
 
                -- If Break implements Wait for Interrupt
 
                --  Replace normal flow with a modified
 
                --  version of INT instruction
 
                if( BRK_Implements_WAI )then
 
                  CPU_Next_State <= WAIT_FOR_INT;
 
                  PC_Ctrl.Oper   <= PC_INCR;
 
                end if;
 
 
              when SOP_JMP  =>
              when SOP_JMP  =>
                CPU_Next_State <= JMP_C1;
                CPU_Next_State <= JMP_C1;
                Cache_Ctrl   <= CACHE_OPER1;
                Cache_Ctrl   <= CACHE_OPER1;
 
 

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