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Line 1... Line 1... 
-- Copyright (c)2006, Jeremy Seth Henry
 
-- Copyright (c)2006,2013 Jeremy Seth Henry
 
-- All rights reserved.
 
-- All rights reserved.
 
--
 
--
 
-- Redistribution and use in source and binary forms, with or without
 
-- Redistribution and use in source and binary forms, with or without
 
-- modification, are permitted provided that the following conditions are met:
 
-- modification, are permitted provided that the following conditions are met:
 
--     * Redistributions of source code must retain the above copyright
 
--     * Redistributions of source code must retain the above copyright
Line 18... Line 18... 
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 
 
--
 
-- VHDL Units :  Open8_CPU
 
-- VHDL Units :  Open8_CPU
 
-- Description:  VHDL model of the V8 uRISC 8-bit processor core
 
-- Description:  VHDL model of a RISC 8-bit processor core loosely based on the
 
 
 
--            :   V8/ARC uRISC instruction set. Requires Open8_pkg.vhd
 
 
 
--            :
 
-- Notes      :  Generic definitions
 
-- Notes      :  Generic definitions
 
--            :  Stack_Start_Address - determines the initial (reset) value of
 
 
 
--            :   the stack pointer. Also used for the RSP instruction if
 
 
 
--            :   Allow_Stack_Address_Move is 0.
 
 
 
--            :
 
--            :
 
--            :  Allow_Stack_Address_Move - When set to 1, allows the RSP to be
 
--            :  Program_Start_Addr - Determines the initial value of the
 
--            :   programmed via thet RSP instruction. If enabled, the contents
 
--            :   program counter.
 
--            :   of R1:R0 are used to initialize the stack pointer.
 
 
 
--            :
 
--            :
 
--            :  ISR_Start_Addr - determines the location of the interrupt
 
--            :  ISR_Start_Addr - determines the location of the interrupt
 
--            :   service vector table. There are 8 service vectors, or 16
 
--            :   service vector table. There are 8 service vectors, or 16
 
--            :   bytes, which must be allocated to either ROM or RAM.
 
--            :   bytes, which must be allocated to either ROM or RAM.
 
--            :
 
--            :
 
--            :  Program_Start_Addr - Determines the initial value of the
 
--            :  Stack_Start_Address - determines the initial (reset) value of
 
--            :   program counter.
 
--            :   the stack pointer. Also used for the RSP instruction if
 
--            :
 
--            :   Allow_Stack_Address_Move is 0.
 
--            :  Default_Interrupt_Mask - Determines the intial value of the
 
 
 
--            :   interrupt mask. To remain true to the original core, which
 
 
 
--            :   had no interrupt mask, this should be set to x"FF". Otherwise
 
 
 
--            :   it can be initialized to any value.
 
 
 
--            :
 
--            :
 
--            :  Enable_CPU_Halt - determines whether the CPU_Halt pin is
 
--            :  Allow_Stack_Address_Move - When set to 1, allows the RSP to be
 
--            :   connected or not. This signal is typically used to halt the
 
--            :   programmed via thet RSP instruction. If enabled, the contents
 
--            :   processor for a few cycles when accessing slower peripherals,
 
--            :   of R1:R0 are used to initialize the stack pointer.
 
--            :   but may also be used to single step the processor. If this
 
 
 
--            :   feature isn't used, it can be disabled to increase Fmax.
 
 
 
--            :
 
 
 
--            :  The CPU_Halt signal can be used to access slower peripherals
 
 
 
--            :   by allowing the device to "pause" the CPU. This can be used,
 
 
 
--            :   for example, to write to a standard LCD panel, which requires
 
 
 
--            :   a 4MHz interface, by halting on writes. Alternately, devices
 
 
 
--            :   such as SDRAM controllers, can pause the processor until the
 
 
 
--            :   data is ready to be presented.
 
 
 
--            :
 
--            :
 
--            :  The Enable_Auto_Increment generic can be used to modify the
 
--            :  The Enable_Auto_Increment generic can be used to modify the
 
--            :   indexed instructions such that specifying an odd register
 
--            :   indexed instructions such that specifying an odd register
 
--            :   will use the next lower register pair, post-incrementing the
 
--            :   will use the next lower register pair, post-incrementing the
 
--            :   value in that pair. IOW, specifying STX R1 will instead
 
--            :   value in that pair. IOW, specifying STX R1 will instead
 
--            :   result in STX R0++, or R0 = {R1:R0}; {R1:R0} + 1
 
--            :   result in STX R0++, or R0 = {R1:R0}; {R1:R0} + 1
 
--            :
 
--            :
 
--            : Instructions USR and USR2 have been replaced with DBNZ, and MUL
 
 
 
--            :  respectively. DBNZ decrements the specified register, and will
 
 
 
--            :  branch if the result is non-zero (Zero flag is not set). MUL
 
 
 
--            :  places the result of R0 * Rn into R1:R0, and executes in two
 
 
 
--            :  cycles. (R1:R0 = R0 * Rn)
 
 
 
--            :
 
 
 
--            : BRK_Implements_WAI modifies the BRK instruction such that it
 
--            : BRK_Implements_WAI modifies the BRK instruction such that it
 
--            :  triggers the wait for interrupt state, but without triggering
 
--            :  triggers the wait for interrupt state, but without triggering
 
--            :  a soft interrupt in lieu of its normal behavior, which is to
 
--            :  a soft interrupt in lieu of its normal behavior, which is to
 
--            :  insert several dead clock cycles - essentially a long NOP
 
--            :  insert several dead clock cycles - essentially a long NOP
 
-- Revision History
 
--            :
 
-- Author          Date     Change
 
--            :  Enable_NMI overrides the mask bit for interrupt 0, creating a
 
------------------ -------- ---------------------------------------------------
 
--            :   non-maskable interrupt at the highest priority.
 
-- Seth Henry      07/19/06 Design Start
 
--            :
 
-- Seth Henry      01/18/11 Fixed BTT instruction to match V8
 
--            :  Default_Interrupt_Mask - Determines the intial value of the
 
-- Seth Henry      07/22/11 Fixed interrupt transition logic to avoid data
 
--            :   interrupt mask. To remain true to the original core, which
 
--                           corruption issues.
 
--            :   had no interrupt mask, this should be set to x"FF". Otherwise
 
-- Seth Henry      07/26/11 Optimized logic in ALU, stack pointer, and data
 
--            :   it can be initialized to any value. Enable_NMI will logically
 
--                           path sections.
 
--            :   force the LSB high.
 
-- Seth Henry      07/27/11 Optimized logic for timing, merged blocks into
 
--            : 
--                           single entity.
 
--            :  Reset_Level - Determines whether the processor registers reset
 
-- Seth Henry      09/20/11 Added BRK_Implements_WAI option, allowing the
 
--            :   on a high or low level from higher logic.
 
--                           processor to wait for an interrupt instead of the
 
--            :
 
--                           normal BRK behavior.
 
--            : Architecture notes
 
-- Seth Henry      12/20/11 Modified core to allow WAIT_FOR_INT state to idle
 
--            :  This model deviates from the original ISA in a few important
 
--                           the bus entirely (Rd_Enable is low)
 
--            :   ways.
 
 
 
--            :
 
 
 
--            :  First, there is only one set of registers. Interrupt service
 
 
 
--            :   routines must explicitely preserve context since the the
 
 
 
--            :   hardware doesn't. This was done to decrease size and code
 
 
 
--            :   complexity. Older code that assumes this behavior will not
 
 
 
--            :   execute correctly on this processor model.
 
 
 
--            :
 
 
 
--            :  Second, this model adds an additional pipeline stage between
 
 
 
--            :   the instruction decoder and the ALU. Unfortunately, this
 
 
 
--            :   means that the instruction stream has to be restarted after
 
 
 
--            :   any math instruction is executed, implying that any ALU
 
 
 
--            :   instruction now has a latency of 2 instead of 0. The
 
 
 
--            :   advantage is that the maximum frequency has gone up
 
 
 
--            :   significantly, as the ALU code is vastly more efficient.
 
 
 
--            :   As an aside, this now means that all math instructions,
 
 
 
--            :   including MUL (see below) and UPP have the same instruction
 
 
 
--            :   latency.
 
 
 
--            :
 
 
 
--            :  Third, the original ISA, also a soft core, had two reserved
 
 
 
--            :   instructions, USR and USR2. These have been implemented as
 
 
 
--            :   DBNZ, and MUL respectively.
 
 
 
--            :
 
 
 
--            :  DBNZ decrements the specified register and branches if the
 
 
 
--            :   result is non-zero. The instruction effectively executes a
 
 
 
--            :   DEC Rn instruction prior to branching, so the same flags will
 
 
 
--            :   be set.
 
 
 
--            :
 
 
 
--            :  MUL places the result of R0 * Rn into R1:R0. Instruction
 
 
 
--            :   latency is identical to other ALU instructions. Only the Z
 
 
 
--            :   flag is set, since there is no defined overflow or "negative
 
 
 
--            :   16-bit values"
 
 
 
--            :
 
 
 
--            :  Fourth, indexed load/store instructions now have an (optional)
 
 
 
--            :   ability to post-increment their index registers. If enabled,
 
 
 
--            :   using an odd operand for LDO,LDX, STO, STX will cause the
 
 
 
--            :   register pair to be incremented after the storage access.
 
 
 
--            :
 
 
 
--            :  Fifth, the RSP instruction has been (optionally) altered to
 
 
 
--            :   allow the stack pointer to be sourced from R1:R0.
 
 
 
--            :
 
 
 
--            :  Sixth, the BRK instruction can optionally implement a WAI,
 
 
 
--            :   which is the same as the INT instruction without the soft
 
 
 
--            :   interrupt, as a way to put the processor to "sleep" until the
 
 
 
--            :   next interrupt.
 
 
 
--            :
 
 
 
--            :  Seventh, the original CPU model had 8 non-maskable interrupts
 
 
 
--            :   with priority. This model has the same 8 interrupts, but
 
 
 
--            :   allows software to mask them (with an additional option to 
 
 
--            :   override the highest priority interrupt, making it the NMI.)
 
 
 
--            :   The interrupt code will retain memory of lower priority
 
 
 
--            :   interrupts, and execute them as it can.
 
 
 
--            :
 
 
 
--            :  Lastly, previous unmapped instructions in the OP_STK opcode
 
 
 
--            :   were repurposed to support a new interrupt mask.
 
 
 
--            :   SMSK and GMSK transfer the contents of R0 (accumulator)
 
 
 
--            :   to/from the interrupt mask register. SMSK is immediate, while
 
 
 
--            :   GMSK has the same overhead as a math instruction.
 
 
 
 
 
library ieee;
 
library ieee;
 
  use ieee.std_logic_1164.all;
 
  use ieee.std_logic_1164.all;
 
  use ieee.std_logic_unsigned.all;
 
  use ieee.std_logic_unsigned.all;
 
  use ieee.std_logic_arith.all;
 
  use ieee.std_logic_misc.all;
 
 
 
 
 
library work;
 
library work;
 
use work.Open8_pkg.all;
 
use work.Open8_pkg.all;
 
 
 
 
 
entity Open8_CPU is
 
entity Open8_CPU is
 
  generic(
 
  generic(
 
 
 
    Program_Start_Addr       : ADDRESS_TYPE := x"0090"; -- Initial PC location
 
 
 
    ISR_Start_Addr           : ADDRESS_TYPE := x"0080"; -- Bottom of ISR vec's
 
    Stack_Start_Addr         : ADDRESS_TYPE := x"007F"; -- Top of Stack
 
    Stack_Start_Addr         : ADDRESS_TYPE := x"007F"; -- Top of Stack
 
    Allow_Stack_Address_Move : boolean      := false;   -- Use Normal v8 RSP
 
    Allow_Stack_Address_Move : boolean      := false;   -- Use Normal v8 RSP
 
 
 
    Enable_Auto_Increment    : boolean      := false;   -- Modify indexed instr
 
    BRK_Implements_WAI       : boolean      := false;   -- BRK -> Wait for Int
 
    BRK_Implements_WAI       : boolean      := false;   -- BRK -> Wait for Int
 
    ISR_Start_Addr           : ADDRESS_TYPE := x"0080"; -- Bottom of ISR vec's
 
    Enable_NMI               : boolean      := true;    -- force mask for int 0
 
    Program_Start_Addr       : ADDRESS_TYPE := x"0090"; -- Initial PC location
 
 
 
    Default_Interrupt_Mask   : DATA_TYPE    := x"FF";   -- Enable all Ints
 
    Default_Interrupt_Mask   : DATA_TYPE    := x"FF";   -- Enable all Ints
 
    Enable_CPU_Halt          : boolean      := false;   -- Disable HALT pin
 
 
 
    Enable_Auto_Increment    : boolean      := false;   -- Modify indexed instr
 
 
 
    Reset_Level              : std_logic    := '0' );   -- Active reset level
 
    Reset_Level              : std_logic    := '0' );   -- Active reset level
 
  port(
 
  port(
 
    Clock                    : in  std_logic;
 
    Clock                    : in  std_logic;
 
    Reset                    : in  std_logic;
 
    Reset                    : in  std_logic;
 
    CPU_Halt                 : in  std_logic := '0';
 
 
 
    Interrupts               : in  INTERRUPT_BUNDLE;
 
    Interrupts               : in  INTERRUPT_BUNDLE;
 
    --
 
    --
 
    Address                  : out ADDRESS_TYPE;
 
    Address                  : out ADDRESS_TYPE;
 
    Rd_Data                  : in  DATA_TYPE;
 
    Rd_Data                  : in  DATA_TYPE;
 
    Rd_Enable                : out std_logic;
 
    Rd_Enable                : out std_logic;
Line 125... Line 160... 
architecture behave of Open8_CPU is
 
architecture behave of Open8_CPU is
 
 
 
 
 
  subtype OPCODE_TYPE  is std_logic_vector(4 downto 0);
 
  subtype OPCODE_TYPE  is std_logic_vector(4 downto 0);
 
  subtype SUBOP_TYPE   is std_logic_vector(2 downto 0);
 
  subtype SUBOP_TYPE   is std_logic_vector(2 downto 0);
 
 
 
 
 
  -- These are all the primary instructions/op-codes (upper 5-bits)
 
  -- All opcodes should be identical to the opcode used by the assembler
 
 
 
  -- In this case, they match the original V8/ARC uRISC ISA
 
  constant OP_INC            : OPCODE_TYPE := "00000";
 
  constant OP_INC            : OPCODE_TYPE := "00000";
 
  constant OP_ADC            : OPCODE_TYPE := "00001";
 
  constant OP_ADC            : OPCODE_TYPE := "00001";
 
  constant OP_TX0            : OPCODE_TYPE := "00010";
 
  constant OP_TX0            : OPCODE_TYPE := "00010";
 
  constant OP_OR             : OPCODE_TYPE := "00011";
 
  constant OP_OR             : OPCODE_TYPE := "00011";
 
  constant OP_AND            : OPCODE_TYPE := "00100";
 
  constant OP_AND            : OPCODE_TYPE := "00100";
Line 146... Line 182... 
  constant OP_CMP            : OPCODE_TYPE := "01111";
 
  constant OP_CMP            : OPCODE_TYPE := "01111";
 
  constant OP_PSH            : OPCODE_TYPE := "10000";
 
  constant OP_PSH            : OPCODE_TYPE := "10000";
 
  constant OP_POP            : OPCODE_TYPE := "10001";
 
  constant OP_POP            : OPCODE_TYPE := "10001";
 
  constant OP_BR0            : OPCODE_TYPE := "10010";
 
  constant OP_BR0            : OPCODE_TYPE := "10010";
 
  constant OP_BR1            : OPCODE_TYPE := "10011";
 
  constant OP_BR1            : OPCODE_TYPE := "10011";
 
  constant OP_DBNZ           : OPCODE_TYPE := "10100"; -- USR
 
  constant OP_DBNZ           : OPCODE_TYPE := "10100";
 
  constant OP_INT            : OPCODE_TYPE := "10101";
 
  constant OP_INT            : OPCODE_TYPE := "10101";
 
  constant OP_MUL            : OPCODE_TYPE := "10110"; -- USR2
 
  constant OP_MUL            : OPCODE_TYPE := "10110";
 
  constant OP_STK            : OPCODE_TYPE := "10111";
 
  constant OP_STK            : OPCODE_TYPE := "10111";
 
  constant OP_UPP            : OPCODE_TYPE := "11000";
 
  constant OP_UPP            : OPCODE_TYPE := "11000";
 
  constant OP_STA            : OPCODE_TYPE := "11001";
 
  constant OP_STA            : OPCODE_TYPE := "11001";
 
  constant OP_STX            : OPCODE_TYPE := "11010";
 
  constant OP_STX            : OPCODE_TYPE := "11010";
 
  constant OP_STO            : OPCODE_TYPE := "11011";
 
  constant OP_STO            : OPCODE_TYPE := "11011";
 
  constant OP_LDI            : OPCODE_TYPE := "11100";
 
  constant OP_LDI            : OPCODE_TYPE := "11100";
 
  constant OP_LDA            : OPCODE_TYPE := "11101";
 
  constant OP_LDA            : OPCODE_TYPE := "11101";
 
  constant OP_LDX            : OPCODE_TYPE := "11110";
 
  constant OP_LDX            : OPCODE_TYPE := "11110";
 
  constant OP_LDO            : OPCODE_TYPE := "11111";
 
  constant OP_LDO            : OPCODE_TYPE := "11111";
 
 
 
 
 
  -- These are all specific sub-opcodes for OP_STK / 0xB8 (lower 3-bits)
 
  -- OP_STK uses the lower 3 bits to further refine the instruction by
 
 
 
  --  repurposing the source register field. These "sub opcodes" are
 
 
 
  --  take the place of the register select for the OP_STK opcode
 
  constant SOP_RSP           : SUBOP_TYPE := "000";
 
  constant SOP_RSP           : SUBOP_TYPE := "000";
 
  constant SOP_RTS           : SUBOP_TYPE := "001";
 
  constant SOP_RTS           : SUBOP_TYPE := "001";
 
  constant SOP_RTI           : SUBOP_TYPE := "010";
 
  constant SOP_RTI           : SUBOP_TYPE := "010";
 
  constant SOP_BRK           : SUBOP_TYPE := "011";
 
  constant SOP_BRK           : SUBOP_TYPE := "011";
 
  constant SOP_JMP           : SUBOP_TYPE := "100";
 
  constant SOP_JMP           : SUBOP_TYPE := "100";
 
  constant SOP_SMSK          : SUBOP_TYPE := "101";
 
  constant SOP_SMSK          : SUBOP_TYPE := "101";
 
  constant SOP_GMSK          : SUBOP_TYPE := "110";
 
  constant SOP_GMSK          : SUBOP_TYPE := "110";
 
  constant SOP_JSR           : SUBOP_TYPE := "111";
 
  constant SOP_JSR           : SUBOP_TYPE := "111";
 
 
 
 
 
  -- Preinitialization is for simulation only - check actual reset conditions
 
 
 
  type CPU_STATES is (
 
  type CPU_STATES is (
 
      -- Instruction fetch & Decode
 
      -- Instruction fetch & Decode
 
    PIPE_FILL_0, PIPE_FILL_1, PIPE_FILL_2, INSTR_DECODE,
 
    PIPE_FILL_0, PIPE_FILL_1, PIPE_FILL_2, INSTR_DECODE,
 
    -- Branching
 
    -- Branching
 
    BRN_C1, DBNZ_C1, JMP_C1, JMP_C2,
 
    BRN_C1, DBNZ_C1, DBNZ_C2, JMP_C1, JMP_C2,
 
    -- Loads
 
    -- Loads
 
    LDA_C1, LDA_C2, LDA_C3, LDA_C4, LDI_C1, LDO_C1, LDX_C1, LDX_C2, LDX_C3,
 
    LDA_C1, LDA_C2, LDA_C3, LDA_C4, LDI_C1,
 
 
 
    LDO_C1, LDX_C1, LDX_C2, LDX_C3, LDX_C4,
 
    -- Stores
 
    -- Stores
 
    STA_C1, STA_C2, STA_C3, STO_C1, STO_C2, STX_C1, STX_C2,
 
    STA_C1, STA_C2, STO_C1, STO_C2, STX_C1, STX_C2,
 
    -- 2-cycle math
 
    -- math
 
    MUL_C1, UPP_C1,
 
    MATH_C1, GMSK_C1, MUL_C1, UPP_C1,
 
    -- Stack
 
    -- Stack
 
    PSH_C1, POP_C1, POP_C2, POP_C3, POP_C4,
 
    PSH_C1, POP_C1, POP_C2, POP_C3, POP_C4,
 
    -- Subroutines & Interrupts
 
    -- Subroutines & Interrupts
 
    WAIT_FOR_INT, ISR_C1, ISR_C2, ISR_C3, JSR_C1, JSR_C2,
 
    WAIT_FOR_INT, ISR_C1, ISR_C2, ISR_C3, JSR_C1, JSR_C2,
 
    RTS_C1, RTS_C2, RTS_C3, RTS_C4, RTS_C5, RTI_C6,
 
    RTS_C1, RTS_C2, RTS_C3, RTS_C4, RTS_C5, RTI_C6,
 
    -- Debugging
 
    -- Debugging
 
    BRK_C1 );
 
    BRK_C1 );
 
 
 
 
 
  type CACHE_MODES is (CACHE_IDLE, CACHE_INSTR, CACHE_OPER1, CACHE_OPER2,
 
  -- To simplify the logic, the first 16 of these should exactly match their
 
                       CACHE_PREFETCH );
 
  --  corresponding Opcodes. This allows the state logic to simply pass the 
 
 
  --  opcode field to the ALU for most math operations.
 
  type PC_MODES is ( PC_IDLE, PC_REV1, PC_REV2, PC_INCR, PC_LOAD );
 
 
 
 
 
 
 
  type PC_CTRL_TYPE is record
 
 
 
    Oper                     : PC_MODES;
 
 
 
    Offset                   : DATA_TYPE;
 
 
 
    Addr                     : ADDRESS_TYPE;
 
 
 
  end record;
 
 
 
 
 
 
 
  type SP_MODES is ( SP_IDLE, SP_RSET, SP_POP, SP_PUSH );
 
 
 
 
 
 
 
  type SP_CTRL_TYPE is record
 
 
 
    Oper                     : SP_MODES;
 
 
 
    Addr                     : ADDRESS_TYPE;
 
 
 
  end record;
 
 
 
 
 
 
 
  type DP_MODES is ( DATA_BUS_IDLE, DATA_RD_MEM,
 
 
 
                     DATA_WR_REG, DATA_WR_FLAG, DATA_WR_PC );
 
 
 
 
 
 
 
  type DATA_CTRL_TYPE is record
 
 
 
    Src                      : DP_MODES;
 
 
 
    Reg                      : SUBOP_TYPE;
 
 
 
  end record;
 
 
 
 
 
 
 
  -- Preinitialization is for simulation only - check actual reset conditions
 
 
 
  constant INT_VECTOR_0      : ADDRESS_TYPE := ISR_Start_Addr;
 
 
 
  constant INT_VECTOR_1      : ADDRESS_TYPE := ISR_Start_Addr+2;
 
 
 
  constant INT_VECTOR_2      : ADDRESS_TYPE := ISR_Start_Addr+4;
 
 
 
  constant INT_VECTOR_3      : ADDRESS_TYPE := ISR_Start_Addr+6;
 
 
 
  constant INT_VECTOR_4      : ADDRESS_TYPE := ISR_Start_Addr+8;
 
 
 
  constant INT_VECTOR_5      : ADDRESS_TYPE := ISR_Start_Addr+10;
 
 
 
  constant INT_VECTOR_6      : ADDRESS_TYPE := ISR_Start_Addr+12;
 
 
 
  constant INT_VECTOR_7      : ADDRESS_TYPE := ISR_Start_Addr+14;
 
 
 
 
 
 
 
  type INT_CTRL_TYPE is record
 
 
 
    Mask_Set                 : std_logic;
 
 
 
    Soft_Ints                : INTERRUPT_BUNDLE;
 
 
 
    Incr_ISR                 : std_logic;
 
 
 
  end record;
 
 
 
 
 
 
 
  type INT_HIST is array (0 to 8) of integer range 0 to 7;
 
 
 
 
 
 
 
  -- Most of the ALU instructions are the same as their Opcode equivalents with
 
 
 
  -- three exceptions (for IDLE, UPP2, and MUL2)
 
 
 
  constant ALU_INC           : OPCODE_TYPE := "00000"; -- x"00"
 
  constant ALU_INC           : OPCODE_TYPE := "00000"; -- x"00"
 
 
 
  constant ALU_UPP1          : OPCODE_TYPE := "00000"; -- Alias of ALU_INC
 
  constant ALU_ADC           : OPCODE_TYPE := "00001"; -- x"01"
 
  constant ALU_ADC           : OPCODE_TYPE := "00001"; -- x"01"
 
  constant ALU_TX0           : OPCODE_TYPE := "00010"; -- x"02"
 
  constant ALU_TX0           : OPCODE_TYPE := "00010"; -- x"02"
 
  constant ALU_OR            : OPCODE_TYPE := "00011"; -- x"03"
 
  constant ALU_OR            : OPCODE_TYPE := "00011"; -- x"03"
 
  constant ALU_AND           : OPCODE_TYPE := "00100"; -- x"04"
 
  constant ALU_AND           : OPCODE_TYPE := "00100"; -- x"04"
 
  constant ALU_XOR           : OPCODE_TYPE := "00101"; -- x"05"
 
  constant ALU_XOR           : OPCODE_TYPE := "00101"; -- x"05"
Line 251... Line 247... 
  constant ALU_STP           : OPCODE_TYPE := "01011"; -- x"0B"
 
  constant ALU_STP           : OPCODE_TYPE := "01011"; -- x"0B"
 
  constant ALU_BTT           : OPCODE_TYPE := "01100"; -- x"0C"
 
  constant ALU_BTT           : OPCODE_TYPE := "01100"; -- x"0C"
 
  constant ALU_CLP           : OPCODE_TYPE := "01101"; -- x"0D"
 
  constant ALU_CLP           : OPCODE_TYPE := "01101"; -- x"0D"
 
  constant ALU_T0X           : OPCODE_TYPE := "01110"; -- x"0E"
 
  constant ALU_T0X           : OPCODE_TYPE := "01110"; -- x"0E"
 
  constant ALU_CMP           : OPCODE_TYPE := "01111"; -- x"0F"
 
  constant ALU_CMP           : OPCODE_TYPE := "01111"; -- x"0F"
 
  constant ALU_POP           : OPCODE_TYPE := "10001"; -- x"11"
 
  constant ALU_IDLE          : OPCODE_TYPE := "10000"; -- x"10"
 
 
 
  constant ALU_UPP2          : OPCODE_TYPE := "10010"; -- x"11"
 
 
 
  constant ALU_RFLG          : OPCODE_TYPE := "10011"; -- x"12"
 
  constant ALU_MUL           : OPCODE_TYPE := "10110"; -- x"16"
 
  constant ALU_MUL           : OPCODE_TYPE := "10110"; -- x"16"
 
  constant ALU_UPP           : OPCODE_TYPE := "11000"; -- x"18"
 
 
 
  constant ALU_LDI           : OPCODE_TYPE := "11100"; -- x"1C"
 
  constant ALU_LDI           : OPCODE_TYPE := "11100"; -- x"1C"
 
  constant ALU_LDX           : OPCODE_TYPE := "11110"; -- x"1E"
 
 
 
 
 
 
 
  constant ALU_IDLE          : OPCODE_TYPE := "10000"; -- x"10"
 
 
 
  constant ALU_UPP2          : OPCODE_TYPE := "10010"; -- x"12"
 
 
 
  constant ALU_RFLG          : OPCODE_TYPE := "10011"; -- x"13"
 
 
 
 
 
 
 
  constant FL_ZERO           : integer := 0;
 
  constant FL_ZERO           : integer := 0;
 
  constant FL_CARRY          : integer := 1;
 
  constant FL_CARRY          : integer := 1;
 
  constant FL_NEG            : integer := 2;
 
  constant FL_NEG            : integer := 2;
 
  constant FL_INT_EN         : integer := 3;
 
  constant FL_INT_EN         : integer := 3;
 
  constant FL_GP1            : integer := 4;
 
  constant FL_GP1            : integer := 4;
 
  constant FL_GP2            : integer := 5;
 
  constant FL_GP2            : integer := 5;
 
  constant FL_GP3            : integer := 6;
 
  constant FL_GP3            : integer := 6;
 
  constant FL_GP4            : integer := 7;
 
  constant FL_GP4            : integer := 7;
 
 
 
 
 
  type ALU_CTRL_TYPE is record
 
 
 
    Oper                     : OPCODE_TYPE;
 
 
 
    Reg                      : SUBOP_TYPE;
 
 
 
    Data                     : DATA_TYPE;
 
 
 
  end record;
 
 
 
 
 
 
 
  constant ACCUM             : SUBOP_TYPE := "000";
 
  constant ACCUM             : SUBOP_TYPE := "000";
 
  constant INT_FLAG          : SUBOP_TYPE := "011";
 
  constant INT_FLAG          : SUBOP_TYPE := "011";
 
 
 
 
 
  type REGFILE_TYPE is array (0 to 7) of DATA_TYPE;
 
  type REGFILE_TYPE is array (0 to 7) of DATA_TYPE;
 
 
 
 
 
  subtype FLAG_TYPE is DATA_TYPE;
 
  subtype FLAG_TYPE is DATA_TYPE;
 
 
 
 
 
  signal Halt                : std_logic;
 
  constant INT_VECTOR_0      : ADDRESS_TYPE := ISR_Start_Addr +  0;
 
 
 
  constant INT_VECTOR_1      : ADDRESS_TYPE := ISR_Start_Addr +  2;
 
 
 
  constant INT_VECTOR_2      : ADDRESS_TYPE := ISR_Start_Addr +  4;
 
 
 
  constant INT_VECTOR_3      : ADDRESS_TYPE := ISR_Start_Addr +  6;
 
 
 
  constant INT_VECTOR_4      : ADDRESS_TYPE := ISR_Start_Addr +  8;
 
 
 
  constant INT_VECTOR_5      : ADDRESS_TYPE := ISR_Start_Addr + 10;
 
 
 
  constant INT_VECTOR_6      : ADDRESS_TYPE := ISR_Start_Addr + 12;
 
 
 
  constant INT_VECTOR_7      : ADDRESS_TYPE := ISR_Start_Addr + 14;
 
 
 
 
 
  signal CPU_Next_State      : CPU_STATES := PIPE_FILL_0;
 
  type CPU_CTRL_TYPE is record
 
  signal CPU_State           : CPU_STATES := PIPE_FILL_0;
 
    State                    : CPU_STATES;
 
 
 
    LS_Address               : ADDRESS_TYPE;
 
 
 
    Program_Ctr              : ADDRESS_TYPE;
 
 
 
    Stack_Ptr                : ADDRESS_TYPE;
 
 
 
    Opcode                   : OPCODE_TYPE;
 
 
 
    SubOp_p0                 : SUBOP_TYPE;
 
 
 
    SubOp_p1                 : SUBOP_TYPE;
 
 
 
    Cache_Valid              : std_logic;
 
 
 
    Prefetch                 : DATA_TYPE;
 
 
 
    Operand1                 : DATA_TYPE;
 
 
 
    Operand2                 : DATA_TYPE;
 
 
 
    AutoIncr                 : std_logic;
 
 
 
    A_Oper                   : OPCODE_TYPE;
 
 
 
    A_Reg                    : SUBOP_TYPE;
 
 
 
    A_Data                   : DATA_TYPE;
 
 
 
    A_NoFlags                : std_logic;
 
 
 
    M_Reg                    : SUBOP_TYPE;
 
 
 
    M_Prod                   : ADDRESS_TYPE;
 
 
 
    Regfile                  : REGFILE_TYPE;
 
 
 
    Flags                    : FLAG_TYPE;
 
 
 
    Int_Mask                 : DATA_TYPE;
 
 
 
    Int_Addr                 : ADDRESS_TYPE;
 
 
 
    Int_Pending              : DATA_TYPE;
 
 
 
    Int_Level                : integer range 0 to 7;
 
 
 
    Wait_for_FSM             : std_logic;
 
 
 
  end record;
 
 
 
 
 
  signal Cache_Ctrl          : CACHE_MODES := CACHE_IDLE;
 
  signal CPU                 : CPU_CTRL_TYPE;
 
 
 
 
 
  signal Opcode              : OPCODE_TYPE := (others => '0');
 
  alias  Accumulator         is CPU.Regfile(0);
 
  signal SubOp, SubOp_p1     : SUBOP_TYPE  := (others => '0');
 
  alias  Flags               is CPU.Flags;
 
 
 
 
 
  signal Prefetch            : DATA_TYPE   := x"00";
 
  signal Ack_Q, Ack_Q1       : std_logic;
 
  signal Operand1, Operand2  : DATA_TYPE   := x"00";
 
  signal Int_Req, Int_Ack    : std_logic;
 
 
 
 
 
  signal Instr_Prefetch      : std_logic   := '0';
 
  type IC_MODES is ( CACHE_IDLE, CACHE_INSTR, CACHE_OPER1, CACHE_OPER2,
 
 
 
                     CACHE_PREFETCH, CACHE_PFFLUSH, CACHE_INVALIDATE );
 
 
 
 
 
  signal PC_Ctrl             : PC_CTRL_TYPE;
 
  type PC_MODES is ( PC_INCR, PC_IDLE, PC_REV1, PC_REV2, PC_REV3,
 
  signal Program_Ctr         : ADDRESS_TYPE := x"0000";
 
                     PC_BRANCH, PC_LOAD );
 
 
 
 
 
  signal SP_Ctrl             : SP_CTRL_TYPE;
 
  type SP_MODES is ( SP_IDLE, SP_RSET, SP_POP, SP_PUSH );
 
  signal Stack_Ptr           : ADDRESS_TYPE := x"0000";
 
 
 
 
 
 
 
  signal DP_Ctrl             : DATA_CTRL_TYPE;
 
  type DP_MODES is ( DATA_BUS_IDLE, DATA_RD_MEM,
 
 
 
                     DATA_WR_REG, DATA_WR_FLAG, DATA_WR_PC );
 
 
 
 
 
  signal INT_Ctrl            : INT_CTRL_TYPE;
 
  type DP_CTRL_TYPE is record
 
  signal Ack_D, Ack_Q, Ack_Q1: std_logic   := '0';
 
    Src                      : DP_MODES;
 
  signal Int_RTI_D, Int_RTI  : std_logic   := '0';
 
    Reg                      : SUBOP_TYPE;
 
  signal Int_Req, Int_Ack    : std_logic   := '0';
 
  end record;
 
  signal Int_Mask            : DATA_TYPE   := x"00";
 
 
 
  signal ISR_Addr            : ADDRESS_TYPE := x"0000";
 
 
 
  signal i_Ints              : INTERRUPT_BUNDLE := x"00";
 
 
 
  signal Pending             : INTERRUPT_BUNDLE := x"00";
 
 
 
  signal Wait_for_FSM        : std_logic := '0';
 
 
 
  signal History             : INT_HIST := (others => 0);
 
 
 
  signal Hst_Ptr             : integer range 0 to 8 := 0;
 
 
 
 
 
 
 
  signal ALU_Ctrl            : ALU_CTRL_TYPE;
 
  type INT_CTRL_TYPE is record
 
  signal Regfile             : REGFILE_TYPE;
 
    Mask_Set                 : std_logic;
 
  signal Flags               : FLAG_TYPE;
 
    Soft_Ints                : INTERRUPT_BUNDLE;
 
  signal Mult                : ADDRESS_TYPE := x"0000";
 
    Incr_ISR                 : std_logic;
 
 
 
  end record;
 
 
 
 
 
begin
 
begin
 
 
 
 
 
Halt_Disabled_fn: if( not Enable_CPU_Halt )generate
 
  Address_Sel: process( CPU )
 
  Halt                       <= '0';
 
    variable Offset_SX       : ADDRESS_TYPE;
 
end generate;
 
  begin
 
 
 
    Offset_SX(15 downto 8)   := (others => CPU.Operand1(7));
 
Halt_Enabled_fn: if( Enable_CPU_Halt )generate
 
    Offset_SX(7 downto 0)    := CPU.Operand1;
 
  Halt                       <= CPU_Halt;
 
 
 
end generate;
 
 
 
 
 
 
 
-------------------------------------------------------------------------------
 
    case( CPU.State )is
 
-- State Logic / Instruction Decoding & Execution
 
      when LDO_C1 | LDX_C1 | STO_C1 | STX_C1 =>
 
-- Combinatorial portion of CPU finite state machine
 
        Address              <= CPU.LS_Address + Offset_SX;
 
-------------------------------------------------------------------------------
 
      when LDA_C2 | STA_C2 =>
 
 
 
        Address              <= (CPU.Operand2 & CPU.Operand1);
 
 
 
      when PSH_C1 | POP_C1 | ISR_C3 | JSR_C1 | JSR_C2 |
 
 
 
           RTS_C1 | RTS_C2 | RTS_C3 =>
 
 
 
        Address              <= CPU.Stack_Ptr;
 
 
 
      when ISR_C1 | ISR_C2 =>
 
 
 
        Address              <= CPU.Int_Addr;
 
 
 
      when others =>
 
 
 
        Address              <= CPU.Program_Ctr;
 
 
 
    end case;
 
 
 
  end process;
 
 
 
 
 
  State_Logic: process(CPU_State, Regfile, Flags, Int_Mask, Opcode,
 
  CPU_Proc: process( Clock, Reset )
 
                       SubOp , SubOp_p1, Operand1, Operand2, Int_Req,
 
    variable IC              : IC_MODES;
 
                       Program_Ctr, Stack_Ptr, ISR_Addr )
 
    variable PC              : PC_MODES;
 
    variable Reg, Reg_1      : integer range 0 to 7 := 0;
 
    variable SP              : SP_MODES;
 
 
 
    variable DP              : DP_CTRL_TYPE;
 
 
 
    variable INT             : INT_CTRL_TYPE;
 
 
 
    variable RegSel          : integer range 0 to 7;
 
 
 
    variable Reg_l, Reg_u    : integer range 0 to 7;
 
 
 
    variable Ack_D           : std_logic;
 
    variable Offset_SX       : ADDRESS_TYPE;
 
    variable Offset_SX       : ADDRESS_TYPE;
 
 
 
    variable Index           : integer range 0 to 7;
 
 
 
    variable Temp            : std_logic_vector(8 downto 0);
 
  begin
 
  begin
 
    CPU_Next_State           <= CPU_State;
 
    if( Reset = Reset_Level )then
 
    Cache_Ctrl               <= CACHE_IDLE;
 
      CPU.State              <= PIPE_FILL_0;
 
    --
 
      CPU.LS_Address         <= (others => '0');
 
    ALU_Ctrl.Oper            <= ALU_IDLE;
 
      CPU.Program_Ctr        <= Program_Start_Addr;
 
    ALU_Ctrl.Reg             <= ACCUM;
 
      CPU.Stack_Ptr          <= Stack_Start_Addr;
 
    ALU_Ctrl.Data            <= x"00";
 
      CPU.Opcode             <= (others => '0');
 
    --
 
      CPU.SubOp_p0           <= (others => '0');
 
    PC_Ctrl.Oper             <= PC_IDLE;
 
      CPU.SubOp_p1           <= (others => '0');
 
    PC_Ctrl.Offset           <= x"03";
 
      CPU.Prefetch           <= (others => '0');
 
    PC_Ctrl.Addr             <= x"0000";
 
      CPU.Operand1           <= (others => '0');
 
    --
 
      CPU.Operand2           <= (others => '0');
 
    SP_Ctrl.Oper             <= SP_IDLE;
 
      CPU.AutoIncr           <= '0';
 
    --
 
      CPU.Cache_Valid        <= '0';
 
    Address                  <= Program_Ctr;
 
      CPU.A_Oper             <= ALU_IDLE;
 
    --
 
      CPU.A_Reg              <= ACCUM;
 
    DP_Ctrl.Src              <= DATA_RD_MEM;
 
      CPU.A_Data             <= x"00";
 
    DP_Ctrl.Reg              <= ACCUM;
 
      CPU.A_NoFlags          <= '0';
 
    --
 
      CPU.M_Reg              <= (others => '0');
 
    INT_Ctrl.Mask_Set        <= '0';
 
      for i in 0 to 7 loop
 
    INT_Ctrl.Soft_Ints       <= x"00";
 
        CPU.Regfile(i)       <= x"00";
 
    INT_Ctrl.Incr_ISR        <= '0';
 
      end loop;
 
    Ack_D                    <= '0';
 
      CPU.Flags              <= (others => '0');
 
    Int_RTI_D                <= '0';
 
      if( Enable_NMI )then
 
 
 
        CPU.Int_Mask         <= Default_Interrupt_Mask(7 downto 1) & '1';
 
    -- Assign the most common value of Reg and Reg1 outside the case structure
 
      else
 
    --  to simplify things.
 
        CPU.Int_Mask         <= Default_Interrupt_Mask;
 
    Reg                      := conv_integer(SubOp);
 
      end if;
 
    Reg_1                    := conv_integer(SubOp_p1);
 
      CPU.Int_Addr           <= (others => '0');
 
    Offset_SX(15 downto 0)   := (others => Operand1(7));
 
      CPU.Int_Pending        <= (others => '0');
 
    Offset_SX(7 downto 0)    := Operand1;
 
      CPU.Int_Level          <= 7;
 
 
 
      CPU.Wait_for_FSM       <= '0';
 
 
 
 
 
    case CPU_State is
 
      Ack_Q                  <= '0';
 
-------------------------------------------------------------------------------
 
      Ack_Q1                 <= '0';
 
-- Initial Instruction fetch & decode
 
      Int_Ack                <= '0';
 
-------------------------------------------------------------------------------
 
      Int_Req                <= '0';
 
 
 
 
 
 
 
      Wr_Data                <= x"00";
 
 
 
      Wr_Enable              <= '0';
 
 
 
      Rd_Enable              <= '1';
 
 
 
    elsif( rising_edge(Clock) )then
 
 
 
 
 
 
 
      IC                     := CACHE_IDLE;
 
 
 
      SP                     := SP_IDLE;
 
 
 
      DP.Src                 := DATA_RD_MEM;
 
 
 
      DP.Reg                 := ACCUM;
 
 
 
      Ack_D                  := '0';
 
 
 
      INT.Mask_Set           := '0';
 
 
 
      INT.Soft_Ints          := x"00";
 
 
 
      INT.Incr_ISR           := '0';
 
 
 
      RegSel                 := conv_integer(CPU.SubOp_p0);
 
 
 
 
 
 
 
      if( Enable_Auto_Increment )then
 
 
 
        Reg_l                := conv_integer(CPU.SubOp_p0(2 downto 1) & '0');
 
 
 
        Reg_u                := conv_integer(CPU.SubOp_p0(2 downto 1) & '1');
 
 
 
      else
 
 
 
        Reg_l                := conv_integer(CPU.SubOp_p0);
 
 
 
        Reg_u                := conv_integer(CPU.SubOp_p1);
 
 
 
      end if;
 
 
 
 
 
 
 
      CPU.LS_Address         <= CPU.Regfile(Reg_u) & CPU.Regfile(Reg_l);
 
 
 
 
 
 
 
      CPU.AutoIncr           <= '0';
 
 
 
      if( Enable_Auto_Increment  )then
 
 
 
        CPU.AutoIncr         <= CPU.SubOp_p0(0);
 
 
 
      end if;
 
 
 
 
 
 
 
      CPU.A_Oper             <= ALU_IDLE;
 
 
 
      CPU.A_Reg              <= ACCUM;
 
 
 
      CPU.A_Data             <= x"00";
 
 
 
      CPU.A_NoFlags          <= '0';
 
 
 
 
 
 
 
      case( CPU.State )is
 
      when PIPE_FILL_0 =>
 
      when PIPE_FILL_0 =>
 
        CPU_Next_State       <= PIPE_FILL_1;
 
          PC                 := PC_INCR;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          CPU.State          <= PIPE_FILL_1;
 
 
 
 
 
      when PIPE_FILL_1 =>
 
      when PIPE_FILL_1 =>
 
        CPU_Next_State       <= PIPE_FILL_2;
 
          PC                 := PC_INCR;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          CPU.State          <= PIPE_FILL_2;
 
 
 
 
 
      when PIPE_FILL_2 =>
 
      when PIPE_FILL_2 =>
 
        CPU_Next_State       <= INSTR_DECODE;
 
          IC                 := CACHE_INSTR;
 
        Cache_Ctrl           <= CACHE_INSTR;
 
          PC                 := PC_INCR;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          CPU.State          <= INSTR_DECODE;
 
 
 
 
 
      when INSTR_DECODE =>
 
-------------------------------------------------------------------------------
 
        CPU_Next_State       <= INSTR_DECODE;
 
-- Instruction Decode and dispatch
 
        Cache_Ctrl           <= CACHE_INSTR;
 
-------------------------------------------------------------------------------
 
 
 
 
 
        case Opcode is
 
        when INSTR_DECODE =>
 
 
 
          IC                 := CACHE_INSTR;
 
 
 
          PC                 := PC_INCR;
 
 
 
          case CPU.Opcode is
 
          when OP_PSH =>
 
          when OP_PSH =>
 
            CPU_Next_State   <= PSH_C1;
 
              IC             := CACHE_PREFETCH;
 
            Cache_Ctrl       <= CACHE_PREFETCH;
 
              PC             := PC_IDLE;
 
            PC_Ctrl.Oper     <= PC_REV1;
 
              DP.Src         := DATA_WR_REG;
 
            DP_Ctrl.Src      <= DATA_WR_REG;
 
              DP.Reg         := CPU.SubOp_p0;
 
            DP_Ctrl.Reg      <= SubOp;
 
              CPU.State      <= PSH_C1;
 
 
 
 
 
          when OP_POP =>
 
          when OP_POP =>
 
            CPU_Next_State   <= POP_C1;
 
              IC             := CACHE_PREFETCH;
 
            Cache_Ctrl       <= CACHE_PREFETCH;
 
              PC             := PC_REV2;
 
            PC_Ctrl.Oper     <= PC_REV2;
 
              SP             := SP_POP;
 
            SP_Ctrl.Oper     <= SP_POP;
 
              CPU.State      <= POP_C1;
 
 
 
 
 
          when OP_BR0 | OP_BR1 =>
 
          when OP_BR0 | OP_BR1 =>
 
            CPU_Next_State   <= BRN_C1;
 
              IC             := CACHE_OPER1;
 
            Cache_Ctrl       <= CACHE_OPER1;
 
              CPU.State      <= BRN_C1;
 
            PC_Ctrl.Oper     <= PC_INCR;
 
 
 
 
 
 
 
          when OP_DBNZ =>
 
          when OP_DBNZ =>
 
            CPU_Next_State   <= DBNZ_C1;
 
              IC             := CACHE_OPER1;
 
            Cache_Ctrl       <= CACHE_OPER1;
 
              CPU.A_Oper     <= ALU_DEC;
 
            PC_Ctrl.Oper     <= PC_INCR;
 
              CPU.A_Reg      <= CPU.SubOp_p0;
 
            ALU_Ctrl.Oper    <= ALU_DEC;
 
              CPU.A_Data     <= CPU.Regfile(RegSel);
 
            ALU_Ctrl.Reg     <= SubOp;
 
              CPU.State      <= DBNZ_C1;
 
 
 
 
 
          when OP_INT =>
 
          when OP_INT =>
 
            PC_Ctrl.Oper     <= PC_INCR;
 
              if( CPU.Int_Mask(RegSel) = '1' )then
 
            -- Make sure the requested interrupt is actually enabled first
 
                CPU.State    <= WAIT_FOR_INT;
 
            if( Int_Mask(Reg) = '1' )then
 
                INT.Soft_Ints(RegSel) := '1';
 
              CPU_Next_State <= WAIT_FOR_INT;
 
 
 
              INT_Ctrl.Soft_Ints(Reg) <= '1';
 
 
 
            end if;
 
            end if;
 
 
 
 
 
          when OP_STK =>
 
          when OP_STK =>
 
            case SubOp is
 
              case CPU.SubOp_p0 is
 
              when SOP_RSP  =>
 
              when SOP_RSP  =>
 
                PC_Ctrl.Oper <= PC_INCR;
 
                  SP         := SP_RSET;
 
                SP_Ctrl.Oper <= SP_RSET;
 
 
 
 
 
 
 
              when SOP_RTS | SOP_RTI =>
 
              when SOP_RTS | SOP_RTI =>
 
                CPU_Next_State <= RTS_C1;
 
                  IC         := CACHE_IDLE;
 
                Cache_Ctrl   <= CACHE_IDLE;
 
                  PC         := PC_IDLE;
 
                SP_Ctrl.Oper <= SP_POP;
 
                  SP         := SP_POP;
 
 
 
                  CPU.State  <= RTS_C1;
 
 
 
 
 
              when SOP_BRK  =>
 
              when SOP_BRK  =>
 
                CPU_Next_State   <= BRK_C1;
 
 
 
                PC_Ctrl.Oper     <= PC_REV2;
 
 
 
                -- If Break implements Wait for Interrupt
 
 
 
                --  Replace normal flow with a modified
 
 
 
                --  version of INT instruction
 
 
 
                if( BRK_Implements_WAI )then
 
                if( BRK_Implements_WAI )then
 
                  CPU_Next_State <= WAIT_FOR_INT;
 
                    CPU.State<= WAIT_FOR_INT;
 
                  PC_Ctrl.Oper   <= PC_INCR;
 
                  else
 
 
 
                    PC       := PC_REV2;
 
 
 
                    CPU.State<= BRK_C1;
 
                end if;
 
                end if;
 
 
 
 
 
              when SOP_JMP  =>
 
              when SOP_JMP  =>
 
                CPU_Next_State <= JMP_C1;
 
                  IC         := CACHE_OPER1;
 
                Cache_Ctrl   <= CACHE_OPER1;
 
                  PC         := PC_IDLE;
 
 
 
                  CPU.State  <= JMP_C1;
 
 
 
 
 
              when SOP_SMSK =>
 
              when SOP_SMSK =>
 
                PC_Ctrl.Oper <= PC_INCR;
 
                  INT.Mask_Set := '1';
 
                INT_Ctrl.Mask_Set <= '1';
 
 
 
 
 
 
 
              when SOP_GMSK =>
 
              when SOP_GMSK =>
 
                PC_Ctrl.Oper <= PC_INCR;
 
                  IC         := CACHE_PREFETCH;
 
                ALU_Ctrl.Oper<= ALU_LDI;
 
                  PC         := PC_REV1;
 
                ALU_Ctrl.Reg <= ACCUM;
 
                  CPU.State  <= GMSK_C1;
 
                ALU_Ctrl.Data<= Int_Mask;
 
 
 
 
 
 
 
              when SOP_JSR =>
 
              when SOP_JSR =>
 
                CPU_Next_State <= JSR_C1;
 
                  IC         := CACHE_OPER1;
 
                Cache_Ctrl   <= CACHE_OPER1;
 
                  PC         := PC_IDLE;
 
                DP_Ctrl.Src  <= DATA_WR_PC;
 
                  DP.Src     := DATA_WR_PC;
 
                DP_Ctrl.Reg  <= ACCUM+1;
 
                  DP.Reg     := ACCUM+1;
 
 
 
                  CPU.State  <= JSR_C1;
 
 
 
 
 
              when others => null;
 
              when others => null;
 
            end case;
 
            end case;
 
 
 
 
 
          when OP_MUL =>
 
          when OP_MUL =>
 
            CPU_Next_State   <= MUL_C1;
 
              IC             := CACHE_PREFETCH;
 
            Cache_Ctrl       <= CACHE_PREFETCH;
 
              PC             := PC_REV1;
 
 
 
              CPU.M_Reg      <= CPU.SubOp_p0;
 
            -- We need to back the PC up by 1, and allow it to refill. An
 
              CPU.State      <= MUL_C1;
 
            --  unfortunate consequence of the pipelining. We can get away with
 
 
 
            --  only 1 extra clock by pre-fetching the next instruction, though
 
 
 
            PC_Ctrl.Oper     <= PC_REV1;
 
 
 
            -- Multiplication is automatic, but requires a single clock cycle.
 
 
 
            --  We need to specify the register for Rn (R1:R0 = R0 * Rn) now,
 
 
 
            --   but will issue the multiply command on the next clock to copy
 
 
 
            --   the results to the specified register.
 
 
 
            ALU_Ctrl.Oper    <= ALU_IDLE;
 
 
 
            ALU_Ctrl.Reg     <= SubOp; -- Rn
 
 
 
 
 
 
 
          when OP_UPP =>
 
          when OP_UPP =>
 
            CPU_Next_State   <= UPP_C1;
 
              IC             := CACHE_PREFETCH;
 
            Cache_Ctrl       <= CACHE_PREFETCH;
 
              PC             := PC_REV1;
 
            PC_Ctrl.Oper     <= PC_REV1;
 
              CPU.A_Oper     <= ALU_UPP1;
 
            ALU_Ctrl.Oper    <= Opcode;
 
              CPU.A_NoFlags  <= '1';
 
            ALU_Ctrl.Reg     <= SubOp;
 
              CPU.A_Reg      <= CPU.SubOp_p0;
 
 
 
              CPU.A_Data     <= CPU.Regfile(RegSel);
 
 
 
              CPU.State      <= UPP_C1;
 
 
 
 
 
          when OP_LDA =>
 
          when OP_LDA =>
 
            CPU_Next_State   <= LDA_C1;
 
              IC             := CACHE_OPER1;
 
            Cache_Ctrl       <= CACHE_OPER1;
 
              PC             := PC_IDLE;
 
 
 
              CPU.State      <= LDA_C1;
 
 
 
 
 
          when OP_LDI =>
 
          when OP_LDI =>
 
            CPU_Next_State   <= LDI_C1;
 
              IC             := CACHE_OPER1;
 
            Cache_Ctrl       <= CACHE_OPER1;
 
              PC             := PC_IDLE;
 
            PC_Ctrl.Oper     <= PC_INCR;
 
              CPU.State      <= LDI_C1;
 
 
 
 
 
          when OP_LDO =>
 
          when OP_LDO =>
 
            CPU_Next_State   <= LDO_C1;
 
              IC             := CACHE_OPER1;
 
            Cache_Ctrl       <= CACHE_OPER1;
 
              PC             := PC_IDLE;
 
            PC_Ctrl.Oper     <= PC_REV2;
 
              CPU.State      <= LDO_C1;
 
 
 
 
 
          when OP_LDX =>
 
          when OP_LDX =>
 
            CPU_Next_State   <= LDX_C1;
 
              IC             := CACHE_PFFLUSH;
 
            PC_Ctrl.Oper     <= PC_REV2;
 
              PC             := PC_REV1;
 
            -- If auto-increment is disabled, use the specified register pair,
 
              CPU.State      <= LDX_C1;
 
            --  otherwise, for an odd:even pair, and issue the first half of
 
 
 
            --  a UPP instruction to the ALU
 
 
 
            if( not Enable_Auto_Increment )then
 
 
 
              Address        <= Regfile(Reg_1) & Regfile(Reg);
 
 
 
            else
 
 
 
              Reg            := conv_integer(SubOp(2 downto 1) & '0');
 
 
 
              Reg_1          := conv_integer(SubOp(2 downto 1) & '1');
 
 
 
              Address        <= Regfile(Reg_1) & Regfile(Reg);
 
 
 
              if( SubOp(0) = '1' )then
 
 
 
                ALU_Ctrl.Oper<= ALU_UPP;
 
 
 
                ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
 
 
 
              end if;
 
 
 
            end if;
 
 
 
 
 
 
 
          when OP_STA =>
 
          when OP_STA =>
 
            CPU_Next_State   <= STA_C1;
 
              IC             := CACHE_OPER1;
 
            Cache_Ctrl       <= CACHE_OPER1;
 
              PC             := PC_IDLE;
 
 
 
              CPU.State      <= STA_C1;
 
 
 
 
 
          when OP_STO =>
 
          when OP_STO =>
 
            CPU_Next_State   <= STO_C1;
 
              IC             := CACHE_OPER1;
 
            Cache_Ctrl       <= CACHE_OPER1;
 
              PC             := PC_REV2;
 
            PC_Ctrl.Oper     <= PC_REV2;
 
              DP.Src         := DATA_WR_REG;
 
            DP_Ctrl.Src      <= DATA_WR_REG;
 
              DP.Reg         := ACCUM;
 
            DP_Ctrl.Reg      <= ACCUM;
 
              CPU.State      <= STO_C1;
 
 
 
 
 
          when OP_STX =>
 
          when OP_STX =>
 
            CPU_Next_State   <= STX_C1;
 
              IC             := CACHE_PFFLUSH;
 
            Cache_Ctrl       <= CACHE_PREFETCH;
 
              PC             := PC_REV2;
 
            PC_Ctrl.Oper     <= PC_REV2;
 
              DP.Src         := DATA_WR_REG;
 
            DP_Ctrl.Src      <= DATA_WR_REG;
 
              DP.Reg         := ACCUM;
 
            DP_Ctrl.Reg      <= ACCUM;
 
              CPU.State      <= STX_C1;
 
 
 
 
 
          when others =>
 
          when others =>
 
            PC_Ctrl.Oper     <= PC_INCR;
 
              IC             := CACHE_PREFETCH;
 
            ALU_Ctrl.Oper    <= Opcode;
 
              PC             := PC_REV1;
 
            ALU_Ctrl.Reg     <= SubOp;
 
              CPU.State      <= MATH_C1;
 
 
 
 
 
        end case;
 
        end case;
 
 
 
 
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- Program Control (BR0_C1, BR1_C1, DBNZ_C1, JMP )
 
-- Program Control (BR0_C1, BR1_C1, DBNZ_C1, JMP )
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
 
 
 
 
      when BRN_C1 =>
 
      when BRN_C1 =>
 
        CPU_Next_State       <= INSTR_DECODE;
 
          if( Flags(RegSel) = CPU.Opcode(0) )then
 
        Cache_Ctrl           <= CACHE_INSTR;
 
            IC               := CACHE_IDLE;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
            PC               := PC_BRANCH;
 
        if( Flags(Reg) = Opcode(0) )then
 
            CPU.State        <= PIPE_FILL_0;
 
          CPU_Next_State     <= PIPE_FILL_0;
 
          else
 
          Cache_Ctrl         <= CACHE_IDLE;
 
            IC               := CACHE_INSTR;
 
          PC_Ctrl.Offset     <= Operand1;
 
            CPU.State        <= INSTR_DECODE;
 
        end if;
 
        end if;
 
 
 
 
 
      when DBNZ_C1 =>
 
      when DBNZ_C1 =>
 
        CPU_Next_State       <= INSTR_DECODE;
 
          IC                 := CACHE_PREFETCH;
 
        Cache_Ctrl           <= CACHE_INSTR;
 
          PC                 := PC_IDLE;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          CPU.State          <= DBNZ_C2;
 
 
 
 
 
 
 
        when DBNZ_C2 =>
 
        if( Flags(FL_ZERO) = '0' )then
 
        if( Flags(FL_ZERO) = '0' )then
 
          CPU_Next_State     <= PIPE_FILL_0;
 
            IC               := CACHE_INVALIDATE;
 
          Cache_Ctrl         <= CACHE_IDLE;
 
            PC               := PC_BRANCH;
 
          PC_Ctrl.Offset     <= Operand1;
 
            CPU.State        <= PIPE_FILL_0;
 
 
 
          else
 
 
 
            PC               := PC_REV1;
 
 
 
            CPU.State        <= PIPE_FILL_1;
 
        end if;
 
        end if;
 
 
 
 
 
      when JMP_C1 =>
 
      when JMP_C1 =>
 
        CPU_Next_State       <= JMP_C2;
 
          IC                 := CACHE_OPER2;
 
        Cache_Ctrl           <= CACHE_OPER2;
 
          PC                 := PC_IDLE;
 
 
 
          CPU.State          <= JMP_C2;
 
 
 
 
 
      when JMP_C2 =>
 
      when JMP_C2 =>
 
        CPU_Next_State       <= PIPE_FILL_0;
 
          PC                 := PC_LOAD;
 
        PC_Ctrl.Oper         <= PC_LOAD;
 
          CPU.State          <= PIPE_FILL_0;
 
        PC_Ctrl.Addr         <= Operand2 & Operand1;
 
 
 
 
 
 
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- Data Storage - Load from memory (LDA, LDI, LDO, LDX)
 
-- Data Storage - Load from memory (LDA, LDI, LDO, LDX)
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
 
 
 
 
      when LDA_C1 =>
 
      when LDA_C1 =>
 
        CPU_Next_State       <= LDA_C2;
 
          IC                 := CACHE_OPER2;
 
        Cache_Ctrl           <= CACHE_OPER2;
 
          PC                 := PC_IDLE;
 
 
 
          CPU.State          <= LDA_C2;
 
 
 
 
 
      when LDA_C2 =>
 
      when LDA_C2 =>
 
        CPU_Next_State       <= LDA_C3;
 
          PC                 := PC_IDLE;
 
        Address              <= Operand2 & Operand1;
 
          CPU.State          <= LDA_C3;
 
 
 
 
 
      when LDA_C3 =>
 
      when LDA_C3 =>
 
        CPU_Next_State       <= LDA_C4;
 
          PC                 := PC_IDLE;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          CPU.State          <= LDA_C4;
 
 
 
 
 
      when LDA_C4 =>
 
      when LDA_C4 =>
 
        CPU_Next_State       <= LDI_C1;
 
          IC                 := CACHE_OPER1;
 
        Cache_Ctrl           <= CACHE_OPER1;
 
          PC                 := PC_INCR;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          CPU.State          <= LDI_C1;
 
 
 
 
 
      when LDI_C1 =>
 
      when LDI_C1 =>
 
        CPU_Next_State       <= INSTR_DECODE;
 
          IC                 := CACHE_PREFETCH;
 
        Cache_Ctrl           <= CACHE_INSTR;
 
          PC                 := PC_INCR;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          CPU.A_Oper         <= ALU_LDI;
 
        ALU_Ctrl.Oper        <= ALU_LDI;
 
          CPU.A_Reg          <= CPU.SubOp_p0;
 
        ALU_Ctrl.Reg         <= SubOp;
 
          CPU.A_Data         <= CPU.Operand1;
 
        ALU_Ctrl.Data        <= Operand1;
 
          CPU.State          <= PIPE_FILL_2;
 
 
 
 
 
      when LDO_C1 =>
 
      when LDO_C1 =>
 
        CPU_Next_State       <= LDX_C1;
 
          IC                 := CACHE_PREFETCH;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          PC                 := PC_REV2;
 
        if( Enable_Auto_Increment )then
 
          RegSel             := conv_integer(CPU.SubOp_p0(2 downto 1) & '0');
 
          Reg                := conv_integer(SubOp(2 downto 1) & '0');
 
          if( Enable_Auto_Increment and CPU.AutoIncr = '1' )then
 
          Reg_1              := conv_integer(SubOp(2 downto 1) & '1');
 
            CPU.A_Oper       <= ALU_UPP1;
 
          Address            <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
 
            CPU.A_Reg        <= CPU.SubOp_p0(2 downto 1) & '0';
 
          if( SubOp(0) = '1' )then
 
            CPU.A_NoFlags    <= '1';
 
            ALU_Ctrl.Oper<= ALU_UPP;
 
            CPU.A_Data       <= CPU.RegFile(RegSel);
 
            ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
 
 
 
          end if;
 
 
 
        else
 
 
 
          Address            <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
 
 
 
        end if;
 
        end if;
 
 
 
          CPU.State          <= LDX_C2;
 
 
 
 
 
      when LDX_C1 =>
 
      when LDX_C1 =>
 
        CPU_Next_State       <= LDX_C2;
 
          PC                 := PC_REV2;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          RegSel             := conv_integer(CPU.SubOp_p0(2 downto 1) & '0');
 
 
 
          if( Enable_Auto_Increment and CPU.AutoIncr = '1' )then
 
 
 
            CPU.A_Oper       <= ALU_UPP1;
 
 
 
            CPU.A_Reg        <= CPU.SubOp_p0(2 downto 1) & '0';
 
 
 
            CPU.A_NoFlags    <= '1';
 
 
 
            CPU.A_Data       <= CPU.Regfile(RegSel);
 
 
 
          end if;
 
 
 
          CPU.State          <= LDX_C2;
 
 
 
 
 
      when LDX_C2 =>
 
      when LDX_C2 =>
 
        CPU_Next_State       <= LDX_C3;
 
          PC                 := PC_INCR;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          RegSel             := conv_integer(CPU.SubOp_p0(2 downto 1) & '1');
 
        Cache_Ctrl           <= CACHE_OPER1;
 
          if( Enable_Auto_Increment and CPU.AutoIncr = '1' )then
 
 
 
            CPU.A_Oper       <= ALU_UPP2;
 
 
 
            CPU.A_Reg        <= CPU.SubOp_p0(2 downto 1) & '1';
 
 
 
            CPU.A_Data       <= CPU.Regfile(RegSel);
 
 
 
          end if;
 
 
 
          CPU.State          <= LDX_C3;
 
 
 
 
 
      when LDX_C3 =>
 
      when LDX_C3 =>
 
        CPU_Next_State       <= INSTR_DECODE;
 
          IC                 := CACHE_OPER1;
 
        Cache_Ctrl           <= CACHE_INSTR;
 
          PC                 := PC_INCR;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          CPU.State          <= LDX_C4;
 
        ALU_Ctrl.Oper        <= ALU_LDX;
 
 
 
        ALU_Ctrl.Reg         <= ACCUM;
 
        when LDX_C4 =>
 
        ALU_Ctrl.Data        <= Operand1;
 
          PC                 := PC_INCR;
 
 
 
          CPU.A_Oper         <= ALU_LDI;
 
 
 
          CPU.A_Reg          <= ACCUM;
 
 
 
          CPU.A_Data         <= CPU.Operand1;
 
 
 
          CPU.State          <= PIPE_FILL_2;
 
 
 
 
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- Data Storage - Store to memory (STA, STO, STX)
 
-- Data Storage - Store to memory (STA, STO, STX)
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
      when STA_C1 =>
 
      when STA_C1 =>
 
        CPU_Next_State       <= STA_C2;
 
          IC                 := CACHE_OPER2;
 
        Cache_Ctrl           <= CACHE_OPER2;
 
          PC                 := PC_IDLE;
 
        DP_Ctrl.Src          <= DATA_WR_REG;
 
          DP.Src             := DATA_WR_REG;
 
        DP_Ctrl.Reg          <= SubOp;
 
          DP.Reg             := CPU.SubOp_p0;
 
 
 
          CPU.State          <= STA_C2;
 
 
 
 
 
      when STA_C2 =>
 
      when STA_C2 =>
 
        CPU_Next_State       <= STA_C3;
 
          IC                 := CACHE_PREFETCH;
 
        Address              <= Operand2 & Operand1;
 
          PC                 := PC_INCR;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          CPU.State          <= PIPE_FILL_1;
 
 
 
 
 
      when STA_C3 =>
 
 
 
        CPU_Next_State       <= PIPE_FILL_2;
 
 
 
        Cache_Ctrl           <= CACHE_PREFETCH;
 
 
 
        PC_Ctrl.Oper         <= PC_INCR;
 
 
 
 
 
 
 
      when STO_C1 =>
 
      when STO_C1 =>
 
        Cache_Ctrl           <= CACHE_PREFETCH;
 
          IC                 := CACHE_PREFETCH;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          PC                 := PC_INCR;
 
        -- If auto-increment is disabled, just load the registers normally
 
          RegSel             := conv_integer(CPU.SubOp_p0(2 downto 1) & '0');
 
        if( not Enable_Auto_Increment )then
 
        if( not Enable_Auto_Increment )then
 
          CPU_Next_State     <= PIPE_FILL_1;
 
            CPU.State        <= PIPE_FILL_1;
 
          Address            <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
 
 
 
        -- Otherwise, enforce the even register rule, and check the LSB to see
 
 
 
        --  if we should perform the auto-increment on the register pair
 
 
 
        else
 
        else
 
          CPU_Next_State     <= PIPE_FILL_0;
 
            CPU.State        <= PIPE_FILL_0;
 
          Reg                := conv_integer(SubOp(2 downto 1) & '0');
 
            if( CPU.AutoIncr = '1' )then
 
          Reg_1              := conv_integer(SubOp(2 downto 1) & '1');
 
              CPU.A_Oper     <= ALU_UPP1;
 
          Address            <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
 
              CPU.A_Reg      <= CPU.SubOp_p0(2 downto 1) & '0';
 
          if( SubOp(0) = '1' )then
 
              CPU.A_NoFlags  <= '1';
 
            CPU_Next_State   <= STO_C2;
 
              CPU.A_Data     <= CPU.Regfile(RegSel);
 
            ALU_Ctrl.Oper    <= ALU_UPP;
 
              CPU.State      <= STO_C2;
 
            ALU_Ctrl.Reg     <= SubOp(2 downto 1) & '0';
 
 
 
          end if;
 
          end if;
 
        end if;
 
        end if;
 
 
 
 
 
      when STO_C2 =>
 
      when STO_C2 =>
 
        CPU_Next_State       <= PIPE_FILL_1;
 
          PC                 := PC_INCR;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          RegSel             := conv_integer(CPU.SubOp_p0(2 downto 1) & '1');
 
        ALU_Ctrl.Oper        <= ALU_UPP2;
 
          CPU.A_Oper         <= ALU_UPP2;
 
        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';
 
          CPU.A_Reg          <= CPU.SubOp_p0(2 downto 1) & '1';
 
 
 
          CPU.A_Data         <= CPU.Regfile(RegSel);
 
 
 
          CPU.State          <= PIPE_FILL_1;
 
 
 
 
 
      when STX_C1 =>
 
      when STX_C1 =>
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          PC                 := PC_INCR;
 
        -- If auto-increment is disabled, just load the registers normally
 
 
 
        if( not Enable_Auto_Increment )then
 
        if( not Enable_Auto_Increment )then
 
          CPU_Next_State     <= PIPE_FILL_1;
 
            CPU.State        <= PIPE_FILL_1;
 
          Address            <= (Regfile(Reg_1) & Regfile(Reg));
 
 
 
        -- Otherwise, enforce the even register rule, and check the LSB to see
 
 
 
        --  if we should perform the auto-increment on the register pair
 
 
 
        else
 
        else
 
          CPU_Next_State     <= PIPE_FILL_1;
 
            RegSel           := conv_integer(CPU.SubOp_p0(2 downto 1) & '0');
 
          Reg                := conv_integer(SubOp(2 downto 1) & '0');
 
            CPU.State        <= PIPE_FILL_1;
 
          Reg_1              := conv_integer(SubOp(2 downto 1) & '1');
 
            if( CPU.AutoIncr = '1' )then
 
          Address            <= (Regfile(Reg_1) & Regfile(Reg));
 
              CPU.A_Oper     <= ALU_UPP1;
 
          if( SubOp(0) = '1' )then
 
              CPU.A_Reg      <= CPU.SubOp_p0(2 downto 1) & '0';
 
            CPU_Next_State   <= STX_C2;
 
              CPU.A_NoFlags  <= '1';
 
            ALU_Ctrl.Oper    <= ALU_UPP;
 
              CPU.A_Data     <= CPU.Regfile(RegSel);
 
            ALU_Ctrl.Reg     <= SubOp(2 downto 1) & '0';
 
              CPU.State      <= STX_C2;
 
          end if;
 
          end if;
 
        end if;
 
        end if;
 
 
 
 
 
      when STX_C2 =>
 
      when STX_C2 =>
 
        CPU_Next_State       <= PIPE_FILL_2;
 
          PC                 := PC_INCR;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          RegSel             := conv_integer(CPU.SubOp_p0(2 downto 1) & '1');
 
        ALU_Ctrl.Oper        <= ALU_UPP2;
 
          CPU.A_Oper         <= ALU_UPP2;
 
        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';
 
          CPU.A_Reg          <= CPU.SubOp_p0(2 downto 1) & '1';
 
 
 
          CPU.A_Data         <= CPU.Regfile(RegSel);
 
-------------------------------------------------------------------------------
 
          CPU.State          <= PIPE_FILL_2;
 
-- Multi-Cycle Math Operations (UPP, MUL)
 
 
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
      -- Because we have to backup the pipeline by 1 to refetch the 2nd
 
-- Multi-Cycle Math Operations
 
      --  instruction/first operand, we have to return through PF2
 
-------------------------------------------------------------------------------
 
 
 
 
 
 
 
        when MATH_C1 =>
 
 
 
          PC                 := PC_INCR;
 
 
 
          CPU.A_Oper         <= CPU.Opcode;
 
 
 
          CPU.A_Reg          <= CPU.SubOp_p0;
 
 
 
          CPU.A_Data         <= CPU.Regfile(RegSel);
 
 
 
          CPU.State          <= PIPE_FILL_2;
 
 
 
 
 
 
 
        when GMSK_C1 =>
 
 
 
          PC                 := PC_INCR;
 
 
 
          CPU.A_Oper         <= ALU_LDI;
 
 
 
          CPU.A_Data         <= CPU.Int_Mask;
 
 
 
          CPU.State          <= PIPE_FILL_2;
 
 
 
 
 
      when MUL_C1 =>
 
      when MUL_C1 =>
 
        CPU_Next_State       <= PIPE_FILL_2;
 
          PC                 := PC_INCR;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          CPU.A_Oper         <= ALU_MUL;
 
        ALU_Ctrl.Oper        <= ALU_MUL;
 
          CPU.State          <= PIPE_FILL_2;
 
 
 
 
 
      when UPP_C1 =>
 
      when UPP_C1 =>
 
        CPU_Next_State       <= PIPE_FILL_2;
 
          PC                 := PC_INCR;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          RegSel             := conv_integer(CPU.SubOp_p1);
 
        ALU_Ctrl.Oper        <= ALU_UPP2;
 
          CPU.A_Oper         <= ALU_UPP2;
 
        ALU_Ctrl.Reg         <= SubOp_p1;
 
          CPU.A_Reg          <= CPU.SubOp_p1;
 
 
 
          CPU.A_Data         <= CPU.Regfile(RegSel);
 
 
 
          CPU.State          <= PIPE_FILL_2;
 
 
 
 
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- Basic Stack Manipulation (PSH, POP, RSP)
 
-- Basic Stack Manipulation (PSH, POP, RSP)
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
      when PSH_C1 =>
 
      when PSH_C1 =>
 
        CPU_Next_State       <= PIPE_FILL_1;
 
          PC                 := PC_REV1;
 
        Address              <= Stack_Ptr;
 
          SP                 := SP_PUSH;
 
        SP_Ctrl.Oper         <= SP_PUSH;
 
          CPU.State          <= PIPE_FILL_1;
 
 
 
 
 
      when POP_C1 =>
 
      when POP_C1 =>
 
        CPU_Next_State       <= POP_C2;
 
          PC                 := PC_IDLE;
 
        Address              <= Stack_Ptr;
 
          CPU.State          <= POP_C2;
 
 
 
 
 
      when POP_C2 =>
 
      when POP_C2 =>
 
        CPU_Next_State       <= POP_C3;
 
          PC                 := PC_IDLE;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          CPU.State          <= POP_C3;
 
 
 
 
 
      when POP_C3 =>
 
      when POP_C3 =>
 
        CPU_Next_State       <= POP_C4;
 
          IC                 := CACHE_OPER1;
 
        Cache_Ctrl           <= CACHE_OPER1;
 
          PC                 := PC_INCR;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          CPU.State          <= POP_C4;
 
 
 
 
 
      when POP_C4 =>
 
      when POP_C4 =>
 
        CPU_Next_State       <= INSTR_DECODE;
 
          PC                 := PC_INCR;
 
        Cache_Ctrl           <= CACHE_INSTR;
 
          CPU.A_Oper         <= ALU_LDI;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          CPU.A_Reg          <= CPU.SubOp_p0;
 
        ALU_Ctrl.Oper        <= ALU_POP;
 
          CPU.A_NoFlags      <= '1';
 
        ALU_Ctrl.Reg         <= SubOp;
 
          CPU.A_Data         <= CPU.Operand1;
 
        ALU_Ctrl.Data        <= Operand1;
 
          CPU.State          <= PIPE_FILL_2;
 
 
 
 
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- Subroutines & Interrupts (RTS, JSR)
 
-- Subroutines & Interrupts (RTS, JSR)
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
      when WAIT_FOR_INT => -- For soft interrupts only, halt the Program_Ctr
 
        when WAIT_FOR_INT =>
 
        DP_Ctrl.Src          <= DATA_BUS_IDLE;
 
          PC                 := PC_IDLE;
 
        CPU_Next_State       <= WAIT_FOR_INT;
 
          DP.Src             := DATA_BUS_IDLE;
 
 
 
          CPU.State          <= WAIT_FOR_INT;
 
 
 
 
 
      when ISR_C1 =>
 
      when ISR_C1 =>
 
        CPU_Next_State       <= ISR_C2;
 
          PC                 := PC_IDLE;
 
        Address              <= ISR_Addr;
 
          INT.Incr_ISR       := '1';
 
        INT_Ctrl.Incr_ISR    <= '1';
 
          CPU.State          <= ISR_C2;
 
 
 
 
 
      when ISR_C2 =>
 
      when ISR_C2 =>
 
        CPU_Next_State       <= ISR_C3;
 
          PC                 := PC_IDLE;
 
        Address              <= ISR_Addr;
 
          DP.Src             := DATA_WR_FLAG;
 
        DP_Ctrl.Src          <= DATA_WR_FLAG;
 
          CPU.State          <= ISR_C3;
 
 
 
 
 
      when ISR_C3 =>
 
      when ISR_C3 =>
 
        CPU_Next_State       <= JSR_C1;
 
          IC                 := CACHE_OPER1;
 
        Cache_Ctrl           <= CACHE_OPER1;
 
          PC                 := PC_IDLE;
 
        Address              <= Stack_Ptr;
 
          SP                 := SP_PUSH;
 
        SP_Ctrl.Oper         <= SP_PUSH;
 
          DP.Src             := DATA_WR_PC;
 
        DP_Ctrl.Src          <= DATA_WR_PC;
 
          DP.Reg             := ACCUM+1;
 
        DP_Ctrl.Reg          <= ACCUM+1;
 
          Ack_D              := '1';
 
        ALU_Ctrl.Oper        <= ALU_STP;
 
          CPU.A_Oper         <= ALU_STP;
 
        ALU_Ctrl.Reg         <= INT_FLAG;
 
          CPU.A_Reg          <= INT_FLAG;
 
        Ack_D                <= '1';
 
          CPU.State          <= JSR_C1;
 
 
 
 
 
      when JSR_C1 =>
 
      when JSR_C1 =>
 
        CPU_Next_State       <= JSR_C2;
 
          IC                 := CACHE_OPER2;
 
        Cache_Ctrl           <= CACHE_OPER2;
 
          PC                 := PC_IDLE;
 
        Address              <= Stack_Ptr;
 
          SP                 := SP_PUSH;
 
        SP_Ctrl.Oper         <= SP_PUSH;
 
          DP.Src             := DATA_WR_PC;
 
        DP_Ctrl.Src          <= DATA_WR_PC;
 
          DP.Reg             := ACCUM;
 
        DP_Ctrl.Reg          <= ACCUM;
 
          CPU.State          <= JSR_C2;
 
 
 
 
 
      when JSR_C2 =>
 
      when JSR_C2 =>
 
        CPU_Next_State       <= PIPE_FILL_0;
 
          SP                 := SP_PUSH;
 
        Address              <= Stack_Ptr;
 
          PC                 := PC_LOAD;
 
        SP_Ctrl.Oper         <= SP_PUSH;
 
          CPU.State          <= PIPE_FILL_0;
 
        PC_Ctrl.Oper         <= PC_LOAD;
 
 
 
        PC_Ctrl.Addr         <= Operand2 & Operand1;
 
 
 
 
 
 
 
      when RTS_C1 =>
 
      when RTS_C1 =>
 
        CPU_Next_State       <= RTS_C2;
 
          PC                 := PC_IDLE;
 
        Address              <= Stack_Ptr;
 
          SP                 := SP_POP;
 
        SP_Ctrl.Oper         <= SP_POP;
 
          CPU.State          <= RTS_C2;
 
 
 
 
 
      when RTS_C2 =>
 
      when RTS_C2 =>
 
        CPU_Next_State       <= RTS_C3;
 
          PC                 := PC_IDLE;
 
        Address              <= Stack_Ptr;
 
          if( CPU.SubOp_p0 = SOP_RTI )then
 
        -- if this is an RTI, then we need to POP the flags
 
            SP               := SP_POP;
 
        if( SubOp = SOP_RTI )then
 
 
 
          SP_Ctrl.Oper       <= SP_POP;
 
 
 
        end if;
 
        end if;
 
 
 
          CPU.State          <= RTS_C3;
 
 
 
 
 
      when RTS_C3 =>
 
      when RTS_C3 =>
 
        CPU_Next_State       <= RTS_C4;
 
          IC                 := CACHE_OPER1;
 
        Cache_Ctrl           <= CACHE_OPER1;
 
          PC                 := PC_IDLE;
 
        -- It doesn't really matter what is on the address bus for RTS, while
 
          CPU.State          <= RTS_C4;
 
        --  it does for RTI, so we make this the default
 
 
 
        Address              <= Stack_Ptr;
 
 
 
 
 
 
 
      when RTS_C4 =>
 
      when RTS_C4 =>
 
        CPU_Next_State       <= RTS_C5;
 
          IC                 := CACHE_OPER2;
 
        Cache_Ctrl           <= CACHE_OPER2;
 
          PC                 := PC_IDLE;
 
 
 
          CPU.State          <= RTS_C5;
 
 
 
 
 
      when RTS_C5 =>
 
      when RTS_C5 =>
 
        CPU_Next_State       <= PIPE_FILL_0;
 
          PC                 := PC_LOAD;
 
        PC_Ctrl.Oper         <= PC_LOAD;
 
          CPU.State          <= PIPE_FILL_0;
 
        PC_Ctrl.Addr         <= Operand2 & Operand1;
 
          if( CPU.SubOp_p0 = SOP_RTI )then
 
        if( SubOp = SOP_RTI )then
 
            IC               := CACHE_OPER1;
 
          CPU_Next_State     <= RTI_C6;
 
            CPU.State        <= RTI_C6;
 
          Cache_Ctrl         <= CACHE_OPER1;
 
 
 
        end if;
 
        end if;
 
 
 
 
 
      when RTI_C6 =>
 
      when RTI_C6 =>
 
        CPU_Next_State       <= PIPE_FILL_1;
 
          PC                 := PC_INCR;
 
        PC_Ctrl.Oper         <= PC_INCR;
 
          CPU.Int_Level      <= 7;
 
        ALU_Ctrl.Oper        <= ALU_RFLG;
 
          CPU.A_Oper         <= ALU_RFLG;
 
        ALU_Ctrl.Data        <= Operand1;
 
          CPU.A_Data         <= CPU.Operand1;
 
        Int_RTI_D            <= '1';
 
          CPU.State          <= PIPE_FILL_1;
 
 
 
 
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- Debugging (BRK) Performs a 5-clock NOP
 
-- Debugging (BRK) Performs a 5-clock NOP
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
 
 
 
 
      when BRK_C1 =>
 
      when BRK_C1 =>
 
        CPU_Next_State       <= PIPE_FILL_0;
 
          PC                 := PC_IDLE;
 
 
 
          CPU.State          <= PIPE_FILL_0;
 
 
 
 
 
      when others =>
 
      when others =>
 
        null;
 
        null;
 
 
 
 
 
    end case;
 
    end case;
 
 
 
 
 
    -- Interrupt service routines can only begin during the decode and wait
 
-------------------------------------------------------------------------------
 
    --  states to avoid corruption due to incomplete instruction execution
 
-- Interrupt Override Logic
 
 
 
-------------------------------------------------------------------------------
 
 
 
 
 
    if( Int_Req = '1' )then
 
    if( Int_Req = '1' )then
 
      if( CPU_State = INSTR_DECODE or CPU_State = WAIT_FOR_INT )then
 
      if( CPU.State = INSTR_DECODE or CPU.State = WAIT_FOR_INT )then
 
        -- Reset all of the sub-block controls to IDLE, to avoid unintended
 
        IC                   := CACHE_IDLE;
 
        --  operation due to the current instruction
 
        PC                   := PC_REV3;
 
        ALU_Ctrl.Oper        <= ALU_IDLE;
 
        SP                   := SP_IDLE;
 
        Cache_Ctrl           <= CACHE_IDLE;
 
        DP.Src               := DATA_RD_MEM;
 
        SP_Ctrl.Oper         <= SP_IDLE;
 
        INT.Soft_Ints        := (others => '0');
 
        DP_Ctrl.Src          <= DATA_RD_MEM; -- JSH 7/20
 
        CPU.A_Oper           <= ALU_IDLE;
 
        INT_Ctrl.Soft_Ints   <= (others => '0'); -- JSH 7/22
 
        CPU.State            <= ISR_C1;
 
        -- Rewind the PC by 3 to compensate for the pipeline registers
 
 
 
        PC_Ctrl.Oper         <= PC_INCR;
 
 
 
        PC_Ctrl.Offset       <= x"FF";
 
 
 
        CPU_Next_State       <= ISR_C1;
 
 
 
 
 
 
 
      end if;
 
      end if;
 
    end if;
 
    end if;
 
 
 
 
 
  end process;
 
-------------------------------------------------------------------------------
 
 
 
-- Vectored Interrupt Controller
 
 
 
-------------------------------------------------------------------------------
 
 
 
 
 
 
 
      CPU.Int_Pending        <= ((Interrupts or INT.Soft_Ints) and
 
 
 
                                 CPU.Int_Mask) or CPU.Int_Pending;
 
 
 
 
 
 
 
      if( CPU.Wait_for_FSM = '0' )then
 
 
 
        if( CPU.Int_Pending(0) = '1' )then
 
 
 
          CPU.Int_Addr       <= INT_VECTOR_0;
 
 
 
          CPU.Int_Level      <= 0;
 
 
 
          CPU.Int_Pending(0) <= '0';
 
 
 
          CPU.Wait_for_FSM   <= '1';
 
 
 
        elsif( CPU.Int_Pending(1) = '1' and CPU.Int_Level > 0 )then
 
 
 
          CPU.Int_Addr       <= INT_VECTOR_1;
 
 
 
          CPU.Int_Level      <= 1;
 
 
 
          CPU.Int_Pending(1) <= '0';
 
 
 
          CPU.Wait_for_FSM   <= '1';
 
 
 
        elsif( CPU.Int_Pending(2) = '1' and CPU.Int_Level > 1 )then
 
 
 
          CPU.Int_Addr       <= INT_VECTOR_2;
 
 
 
          CPU.Int_Level      <= 2;
 
 
 
          CPU.Int_Pending(2) <= '0';
 
 
 
          CPU.Wait_for_FSM   <= '1';
 
 
 
        elsif( CPU.Int_Pending(3) = '1' and CPU.Int_Level > 2 )then
 
 
 
          CPU.Int_Addr       <= INT_VECTOR_3;
 
 
 
          CPU.Int_Level      <= 3;
 
 
 
          CPU.Int_Pending(3) <= '0';
 
 
 
          CPU.Wait_for_FSM   <= '1';
 
 
 
        elsif( CPU.Int_Pending(4) = '1' and CPU.Int_Level > 3 )then
 
 
 
          CPU.Int_Addr       <= INT_VECTOR_4;
 
 
 
          CPU.Int_Level      <= 4;
 
 
 
          CPU.Int_Pending(4) <= '0';
 
 
 
          CPU.Wait_for_FSM   <= '1';
 
 
 
        elsif( CPU.Int_Pending(5) = '1' and CPU.Int_Level > 4 )then
 
 
 
          CPU.Int_Addr       <= INT_VECTOR_5;
 
 
 
          CPU.Int_Level      <= 5;
 
 
 
          CPU.Int_Pending(5) <= '0';
 
 
 
          CPU.Wait_for_FSM   <= '1';
 
 
 
        elsif( CPU.Int_Pending(6) = '1' and CPU.Int_Level > 6 )then
 
 
 
          CPU.Int_Addr       <= INT_VECTOR_6;
 
 
 
          CPU.Int_Level      <= 6;
 
 
 
          CPU.Int_Pending(6) <= '0';
 
 
 
          CPU.Wait_for_FSM   <= '1';
 
 
 
        elsif( CPU.Int_Pending(7) = '1' )then
 
 
 
          CPU.Int_Addr       <= INT_VECTOR_7;
 
 
 
          CPU.Int_Level      <= 7;
 
 
 
          CPU.Int_Pending(7) <= '0';
 
 
 
          CPU.Wait_for_FSM   <= '1';
 
 
 
        end if;
 
 
 
      end if;
 
 
 
 
 
  -- We need to infer a hardware multipler, so we create a special clocked
 
      Ack_Q                  <= Ack_D;
 
  --  process with no reset or clock enable
 
      Ack_Q1                 <= Ack_Q;
 
  Multiplier_proc: process( Clock )
 
      Int_Ack                <= Ack_Q1;
 
  begin
 
      if( Int_Ack = '1' )then
 
    if( rising_edge(Clock) )then
 
        CPU.Wait_for_FSM     <= '0';
 
      Mult                   <= Regfile(0) *
 
      end if;
 
                                Regfile(conv_integer(ALU_Ctrl.Reg));
 
 
 
 
 
      Int_Req                <= CPU.Wait_for_FSM and (not Int_Ack);
 
 
 
 
 
 
 
      if( INT.Mask_Set = '1' )then
 
 
 
        if( Enable_NMI )then
 
 
 
          CPU.Int_Mask       <= Accumulator(7 downto 1) & '1';
 
 
 
        else -- Disable NMI override
 
 
 
          CPU.Int_Mask       <= Accumulator;
 
 
 
        end if;
 
 
 
      end if;
 
 
 
 
 
 
 
      if( INT.Incr_ISR = '1' )then
 
 
 
        CPU.Int_Addr         <= CPU.Int_Addr + 1;
 
    end if;
 
    end if;
 
  end process;
 
 
 
 
 
 
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- Registered portion of CPU finite state machine
 
-- ALU (Arithmetic / Logic Unit)
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
  CPU_Regs: process( Reset, Clock )
 
      Index                  := conv_integer(CPU.A_Reg);
 
    variable Offset_SX       : ADDRESS_TYPE;
 
 
 
    variable i_Ints          : INTERRUPT_BUNDLE := (others => '0');
 
 
 
    variable Sum             : std_logic_vector(8 downto 0) := "000000000";
 
 
 
    variable Index           : integer range 0 to 7 := 0;
 
 
 
    variable Temp            : std_logic_vector(8 downto 0);
 
 
 
  begin
 
 
 
    if( Reset = Reset_Level )then
 
 
 
      CPU_State              <= PIPE_FILL_0;
 
 
 
      Opcode                 <= OP_INC;
 
 
 
      SubOp                  <= ACCUM;
 
 
 
      SubOp_p1               <= ACCUM;
 
 
 
      Operand1               <= x"00";
 
 
 
      Operand2               <= x"00";
 
 
 
      Instr_Prefetch         <= '0';
 
 
 
      Prefetch               <= x"00";
 
 
 
 
 
 
 
      Wr_Data                <= (others => '0');
 
      CPU.M_Prod             <= Accumulator *
 
      Wr_Enable              <= '0';
 
                                CPU.Regfile(conv_integer(CPU.M_Reg));
 
      Rd_Enable              <= '1';
 
 
 
 
 
 
 
      Program_Ctr            <= Program_Start_Addr;
 
      case( CPU.A_Oper )is
 
      Stack_Ptr              <= Stack_Start_Addr;
 
        when ALU_INC => -- Rn = Rn + 1 : CPU.Flags N,C,Z
 
 
 
          Temp               := ("0" & x"01") +
 
 
 
                                ("0" & CPU.A_Data);
 
 
 
          Flags(FL_CARRY)    <= Temp(8);
 
 
 
          CPU.Regfile(Index) <= Temp(7 downto 0);
 
 
 
          if( CPU.A_NoFlags = '0' )then
 
 
 
            Flags(FL_ZERO)   <= nor_reduce(Temp(7 downto 0));
 
 
 
            Flags(FL_NEG)    <= Temp(7);
 
 
 
          end if;
 
 
 
 
 
      Ack_Q                  <= '0';
 
        when ALU_UPP2 => -- Rn = Rn + C : Flags C
 
      Ack_Q1                 <= '0';
 
          Temp               := ("0" & x"00") +
 
      Int_Ack                <= '0';
 
                                ("0" & CPU.A_Data) +
 
      Int_RTI                <= '0';
 
                                 Flags(FL_CARRY);
 
 
 
          Flags(FL_CARRY)    <= Temp(8);
 
 
 
          CPU.Regfile(Index) <= Temp(7 downto 0);
 
 
 
 
 
      Int_Req                <= '0';
 
        when ALU_ADC => -- R0 = R0 + Rn + C :  N,C,Z
 
      Pending                <= x"00";
 
          Temp               := ("0" & Accumulator) +
 
      Wait_for_FSM           <= '0';
 
                                ("0" & CPU.A_Data) +
 
      Int_Mask               <= Default_Interrupt_Mask(7 downto 1) & '1';
 
                                Flags(FL_CARRY);
 
      ISR_Addr               <= INT_VECTOR_0;
 
          Flags(FL_ZERO)     <= nor_reduce(Temp(7 downto 0));
 
      for i in 0 to 8 loop
 
          Flags(FL_CARRY)    <= Temp(8);
 
        History(i)           <= 0;
 
          Flags(FL_NEG)      <= Temp(7);
 
      end loop;
 
          Accumulator        <= Temp(7 downto 0);
 
      Hst_Ptr                <= 0;
 
 
 
 
 
 
 
      for i in 0 to 7 loop
 
        when ALU_TX0 => -- R0 = Rn : Flags N,Z
 
        Regfile(i)           <= (others => '0');
 
          Temp               := "0" & CPU.A_Data;
 
      end loop;
 
          Flags(FL_ZERO)     <= nor_reduce(Temp(7 downto 0));
 
      Flags                  <= x"00";
 
          Flags(FL_NEG)      <= Temp(7);
 
 
 
          Accumulator        <= Temp(7 downto 0);
 
 
 
 
 
    elsif( rising_edge(Clock) )then
 
        when ALU_OR  => -- R0 = R0 | Rn : Flags N,Z
 
      Wr_Enable              <= '0';
 
          Temp(7 downto 0)   := Accumulator or CPU.A_Data;
 
      Wr_Data                <= x"00";
 
          Flags(FL_ZERO)     <= nor_reduce(Temp(7 downto 0));
 
      Rd_Enable              <= '0';
 
          Flags(FL_NEG)      <= Temp(7);
 
 
 
          Accumulator        <= Temp(7 downto 0);
 
 
 
 
 
 
 
        when ALU_AND => -- R0 = R0 & Rn : Flags N,Z
 
 
 
          Temp(7 downto 0)   := Accumulator and CPU.A_Data;
 
 
 
          Flags(FL_ZERO)     <= nor_reduce(Temp(7 downto 0));
 
 
 
          Flags(FL_NEG)      <= Temp(7);
 
 
 
          Accumulator        <= Temp(7 downto 0);
 
 
 
 
 
 
 
        when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z
 
 
 
          Temp(7 downto 0)   := Accumulator xor CPU.A_Data;
 
 
 
          Flags(FL_ZERO)     <= nor_reduce(Temp(7 downto 0));
 
 
 
          Flags(FL_NEG)      <= Temp(7);
 
 
 
          Accumulator        <= Temp(7 downto 0);
 
 
 
 
 
 
 
        when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z
 
 
 
          Temp               := CPU.A_Data & Flags(FL_CARRY);
 
 
 
          Flags(FL_ZERO)     <= nor_reduce(Temp(7 downto 0));
 
 
 
          Flags(FL_CARRY)    <= Temp(8);
 
 
 
          Flags(FL_NEG)      <= Temp(7);
 
 
 
          CPU.Regfile(Index) <= Temp(7 downto 0);
 
 
 
 
 
 
 
        when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z
 
 
 
          Temp               := CPU.A_Data(0) & Flags(FL_CARRY) &
 
 
 
                                CPU.A_Data(7 downto 1);
 
 
 
          Flags(FL_ZERO)     <= nor_reduce(Temp(7 downto 0));
 
 
 
          Flags(FL_CARRY)    <= Temp(8);
 
 
 
          Flags(FL_NEG)      <= Temp(7);
 
 
 
          CPU.Regfile(Index) <= Temp(7 downto 0);
 
 
 
 
 
 
 
        when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
 
 
 
          Temp               := ("0" & CPU.A_Data) +
 
 
 
                                ("0" & x"FF");
 
 
 
          Flags(FL_ZERO)     <= nor_reduce(Temp(7 downto 0));
 
 
 
          Flags(FL_CARRY)    <= Temp(8);
 
 
 
          Flags(FL_NEG)      <= Temp(7);
 
 
 
          CPU.Regfile(Index) <= Temp(7 downto 0);
 
 
 
 
 
 
 
        when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
 
 
 
          Temp               := ("0" & Accumulator) +
 
 
 
                                ("0" & (not CPU.A_Data)) +
 
 
 
                                     Flags(FL_CARRY);
 
 
 
          Flags(FL_ZERO)     <= nor_reduce(Temp(7 downto 0));
 
 
 
          Flags(FL_CARRY)    <= Temp(8);
 
 
 
          Flags(FL_NEG)      <= Temp(7);
 
 
 
          Accumulator        <= Temp(7 downto 0);
 
 
 
 
 
 
 
        when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z
 
 
 
          Temp               := ("0" & Accumulator) +
 
 
 
                                ("0" & CPU.A_Data);
 
 
 
          Flags(FL_CARRY)    <= Temp(8);
 
 
 
          Accumulator        <= Temp(7 downto 0);
 
 
 
          Flags(FL_ZERO)     <= nor_reduce(Temp(7 downto 0));
 
 
 
          Flags(FL_NEG)      <= Temp(7);
 
 
 
 
 
 
 
        when ALU_STP => -- Sets bit(n) in the CPU.Flags register
 
 
 
          Flags(Index)       <= '1';
 
 
 
 
 
 
 
        when ALU_BTT => -- Z = !R0(N), N = R0(7)
 
 
 
          Flags(FL_ZERO)     <= not Accumulator(Index);
 
 
 
          Flags(FL_NEG)      <= Accumulator(7);
 
 
 
 
 
 
 
        when ALU_CLP => -- Clears bit(n) in the Flags register
 
 
 
          Flags(Index)       <= '0';
 
 
 
 
 
 
 
        when ALU_T0X => -- Rn = R0 : Flags N,Z
 
 
 
          Temp               := "0" & Accumulator;
 
 
 
          Flags(FL_ZERO)     <= nor_reduce(Temp(7 downto 0));
 
 
 
          Flags(FL_NEG)      <= Temp(7);
 
 
 
          CPU.Regfile(Index) <= Temp(7 downto 0);
 
 
 
 
 
 
 
        when ALU_CMP => -- Sets CPU.Flags on R0 - Rn : Flags N,C,Z
 
 
 
          Temp               := ("0" & Accumulator) +
 
 
 
                                ("0" & (not CPU.A_Data)) +
 
 
 
                                 '1';
 
 
 
          Flags(FL_ZERO)     <= nor_reduce(Temp(7 downto 0));
 
 
 
          Flags(FL_CARRY)    <= Temp(8);
 
 
 
          Flags(FL_NEG)      <= Temp(7);
 
 
 
 
 
 
 
        when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
 
 
 
          CPU.Regfile(0)     <= CPU.M_Prod(7 downto 0);
 
 
 
          CPU.Regfile(1)     <= CPU.M_Prod(15 downto 8);
 
 
 
          Flags(FL_ZERO)     <= nor_reduce(CPU.M_Prod);
 
 
 
 
 
 
 
        when ALU_LDI => -- Rn <= Data : Flags N,Z
 
 
 
          if( CPU.A_NoFlags = '0' )then
 
 
 
            Flags(FL_ZERO)   <= nor_reduce(CPU.A_Data);
 
 
 
            Flags(FL_NEG)    <= CPU.A_Data(7);
 
 
 
          end if;
 
 
 
          CPU.Regfile(Index) <= CPU.A_Data;
 
 
 
 
 
 
 
        when ALU_RFLG =>
 
 
 
          Flags              <= CPU.A_Data;
 
 
 
 
 
 
 
        when others =>
 
 
 
          null;
 
 
 
      end case;
 
 
 
 
 
      if( Halt = '0' )then
 
 
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- Instruction/Operand caching for pipelined memory access
 
-- Instruction/Operand caching for pipelined memory access
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
        CPU_State            <= CPU_Next_State;
 
 
 
        case Cache_Ctrl is
 
      case( IC )is
 
          when CACHE_INSTR =>
 
          when CACHE_INSTR =>
 
            Opcode           <= Rd_Data(7 downto 3);
 
          CPU.Opcode         <= Rd_Data(7 downto 3);
 
            SubOp            <= Rd_Data(2 downto 0);
 
          CPU.SubOp_p0       <= Rd_Data(2 downto 0);
 
            SubOp_p1         <= Rd_Data(2 downto 0) + 1;
 
          CPU.SubOp_p1       <= Rd_Data(2 downto 0) + 1;
 
            if( Instr_Prefetch = '1' )then
 
          if( CPU.Cache_Valid = '1' )then
 
              Opcode         <= Prefetch(7 downto 3);
 
            CPU.Opcode       <= CPU.Prefetch(7 downto 3);
 
              SubOp          <= Prefetch(2 downto 0);
 
            CPU.SubOp_p0     <= CPU.Prefetch(2 downto 0);
 
              SubOp_p1       <= Prefetch(2 downto 0) + 1;
 
            CPU.SubOp_p1     <= CPU.Prefetch(2 downto 0) + 1;
 
              Instr_Prefetch <= '0';
 
            CPU.Cache_Valid  <= '0';
 
            end if;
 
            end if;
 
 
 
 
 
          when CACHE_OPER1 =>
 
          when CACHE_OPER1 =>
 
            Operand1         <= Rd_Data;
 
          CPU.Operand1       <= Rd_Data;
 
 
 
 
 
          when CACHE_OPER2 =>
 
          when CACHE_OPER2 =>
 
            Operand2         <= Rd_Data;
 
          CPU.Operand2       <= Rd_Data;
 
 
 
 
 
          when CACHE_PREFETCH =>
 
          when CACHE_PREFETCH =>
 
            Prefetch         <= Rd_Data;
 
          CPU.Prefetch       <= Rd_Data;
 
            Instr_Prefetch   <= '1';
 
          CPU.Cache_Valid    <= '1';
 
 
 
 
 
 
 
        when CACHE_PFFLUSH =>
 
 
 
          CPU.Prefetch       <= Rd_Data;
 
 
 
          CPU.Operand1       <= x"00";
 
 
 
          CPU.Operand2       <= x"00";
 
 
 
          CPU.Cache_Valid    <= '1';
 
 
 
 
 
 
 
        when CACHE_INVALIDATE =>
 
 
 
          CPU.Cache_Valid    <= '0';
 
 
 
 
 
          when CACHE_IDLE =>
 
          when CACHE_IDLE =>
 
            null;
 
            null;
 
        end case;
 
        end case;
 
 
 
 
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- Program Counter
 
-- Program Counter
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
        Offset_SX(15 downto 8) := (others => PC_Ctrl.Offset(7));
 
 
 
        Offset_SX(7 downto 0)  := PC_Ctrl.Offset;
 
 
 
 
 
 
 
        case PC_Ctrl.Oper is
 
      Offset_SX(15 downto 8) := (others => CPU.Operand1(7));
 
 
 
      Offset_SX(7 downto 0)  := CPU.Operand1;
 
 
 
 
 
 
 
      case( PC )is
 
 
 
 
 
 
 
        when PC_INCR =>
 
 
 
          CPU.Program_Ctr    <= CPU.Program_ctr + 1;
 
 
 
 
 
          when PC_IDLE =>
 
          when PC_IDLE =>
 
 
 
        --CPU.Program_Ctr    <= CPU.Program_Ctr + 0;
 
            null;
 
            null;
 
 
 
 
 
          when PC_REV1 =>
 
          when PC_REV1 =>
 
            Program_Ctr      <= Program_Ctr - 1;
 
          CPU.Program_Ctr    <= CPU.Program_Ctr - 1;
 
 
 
 
 
          when PC_REV2 =>
 
          when PC_REV2 =>
 
            Program_Ctr      <= Program_Ctr - 2;
 
          CPU.Program_Ctr    <= CPU.Program_Ctr - 2;
 
 
 
 
 
          when PC_INCR =>
 
        when PC_REV3 =>
 
            Program_Ctr      <= Program_Ctr + Offset_SX - 2;
 
          CPU.Program_Ctr    <= CPU.Program_Ctr - 3;
 
 
 
 
 
 
 
        when PC_BRANCH =>
 
 
 
          CPU.Program_Ctr    <= CPU.Program_Ctr + Offset_SX - 2;
 
 
 
 
 
          when PC_LOAD =>
 
          when PC_LOAD =>
 
            Program_Ctr      <= PC_Ctrl.Addr;
 
          CPU.Program_Ctr    <= CPU.Operand2 & CPU.Operand1;
 
 
 
 
 
          when others =>
 
          when others =>
 
            null;
 
            null;
 
        end case;
 
        end case;
 
 
 
 
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- (Write) Data Path
 
-- (Write) Data Path
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
        case DP_Ctrl.Src is
 
 
 
 
 
      Wr_Data                <= x"00";
 
 
 
      Wr_Enable              <= '0';
 
 
 
      Rd_Enable              <= '0';
 
 
 
 
 
 
 
      case( DP.Src )is
 
          when DATA_BUS_IDLE =>
 
          when DATA_BUS_IDLE =>
 
            null;
 
            null;
 
 
 
 
 
          when DATA_RD_MEM =>
 
          when DATA_RD_MEM =>
 
            Rd_Enable        <= '1';
 
            Rd_Enable        <= '1';
 
 
 
 
 
          when DATA_WR_REG =>
 
          when DATA_WR_REG =>
 
            Wr_Enable        <= '1';
 
            Wr_Enable        <= '1';
 
            Wr_Data          <= Regfile(conv_integer(DP_Ctrl.Reg));
 
          Wr_Data            <= CPU.Regfile(conv_integer(DP.Reg));
 
 
 
 
 
          when DATA_WR_FLAG =>
 
          when DATA_WR_FLAG =>
 
            Wr_Enable        <= '1';
 
            Wr_Enable        <= '1';
 
            Wr_Data          <= Flags;
 
            Wr_Data          <= Flags;
 
 
 
 
 
          when DATA_WR_PC =>
 
          when DATA_WR_PC =>
 
            Wr_Enable        <= '1';
 
            Wr_Enable        <= '1';
 
            Wr_Data          <= Program_Ctr(15 downto 8);
 
          Wr_Data            <= CPU.Program_Ctr(15 downto 8);
 
            if( DP_Ctrl.Reg = ACCUM )then
 
          if( DP.Reg = ACCUM )then
 
              Wr_Data        <= Program_Ctr(7 downto 0);
 
            Wr_Data          <= CPU.Program_Ctr(7 downto 0);
 
            end if;
 
            end if;
 
 
 
 
 
          when others =>
 
          when others =>
 
            null;
 
            null;
 
        end case;
 
        end case;
 
 
 
 
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- Stack Pointer
 
-- Stack Pointer
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
        case SP_Ctrl.Oper is
 
      case( SP )is
 
          when SP_IDLE =>
 
          when SP_IDLE =>
 
            null;
 
            null;
 
 
 
 
 
          when SP_RSET =>
 
          when SP_RSET =>
 
-- The original RSP instruction simply reset the stack pointer to the preset
 
          CPU.Stack_Ptr      <= Stack_Start_Addr;
 
--  address set at compile time. However, with little extra effort, we can
 
 
 
--  modify the instruction to allow the stack pointer to be moved anywhere in
 
 
 
--  the memory map. Since RSP can't have an sub-opcode, R1:R0 was chosen as
 
 
 
--  a fixed source
 
 
 
            Stack_Ptr        <= Stack_Start_Addr;
 
 
 
            if( Allow_Stack_Address_Move )then
 
            if( Allow_Stack_Address_Move )then
 
              Stack_Ptr      <= Regfile(1) & Regfile(0);
 
            CPU.Stack_Ptr    <= CPU.Regfile(1) & CPU.Regfile(0);
 
            end if;
 
            end if;
 
 
 
 
 
          when SP_POP  =>
 
          when SP_POP  =>
 
            Stack_Ptr        <= Stack_Ptr + 1;
 
          CPU.Stack_Ptr      <= CPU.Stack_Ptr + 1;
 
 
 
 
 
          when SP_PUSH =>
 
          when SP_PUSH =>
 
            Stack_Ptr        <= Stack_Ptr - 1;
 
          CPU.Stack_Ptr      <= CPU.Stack_Ptr - 1;
 
 
 
 
 
          when others =>
 
          when others =>
 
            null;
 
            null;
 
 
 
 
 
        end case;
 
        end case;
 
 
 
 
 
-------------------------------------------------------------------------------
 
 
 
-- Interrupt Controller
 
 
 
-------------------------------------------------------------------------------
 
 
 
        -- The interrupt control mask is always sourced out of R0
 
 
 
        if( INT_Ctrl.Mask_Set = '1' )then
 
 
 
          Int_Mask           <= Regfile(conv_integer(ACCUM))(7 downto 1) & '1';
 
 
 
        end if;
 
 
 
 
 
 
 
        -- Combine external and internal interrupts, and mask the OR or the two
 
 
 
        --  with the mask. Record any incoming interrupts to the pending buffer
 
 
 
        i_Ints               := (Interrupts or INT_Ctrl.Soft_Ints) and
 
 
 
                                Int_Mask;
 
 
 
        if( i_Ints > 0 )then
 
 
 
          Pending            <= i_Ints;
 
 
 
        end if;
 
 
 
 
 
 
 
        -- Only mess with interrupt signals while the CPU core is not currently
 
 
 
        --  working with, or loading, an ISR address
 
 
 
        if( Wait_for_FSM = '0' and Pending > 0 )then
 
 
 
          if(   Pending(0) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 0))then
 
 
 
            ISR_Addr         <= INT_VECTOR_0;
 
 
 
            Pending(0)       <= '0';
 
 
 
            History(Hst_Ptr+1) <= 0;
 
 
 
            Hst_Ptr          <= Hst_Ptr + 1;
 
 
 
            Wait_for_FSM     <= '1';
 
 
 
          elsif(Pending(1) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 1))then
 
 
 
            ISR_Addr         <= INT_VECTOR_1;
 
 
 
            Pending(1)       <= '0';
 
 
 
            History(Hst_Ptr+1) <= 1;
 
 
 
            Hst_Ptr          <= Hst_Ptr + 1;
 
 
 
            Wait_for_FSM     <= '1';
 
 
 
          elsif(Pending(2) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 2))then
 
 
 
            ISR_Addr         <= INT_VECTOR_2;
 
 
 
            Pending(2)       <= '0';
 
 
 
            History(Hst_Ptr+1) <= 1;
 
 
 
            Hst_Ptr          <= Hst_Ptr + 1;
 
 
 
            Wait_for_FSM     <= '1';
 
 
 
          elsif(Pending(3) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 3))then
 
 
 
            ISR_Addr         <= INT_VECTOR_3;
 
 
 
            Pending(3)       <= '0';
 
 
 
            History(Hst_Ptr+1) <= 3;
 
 
 
            Hst_Ptr          <= Hst_Ptr + 1;
 
 
 
            Wait_for_FSM     <= '1';
 
 
 
          elsif(Pending(4) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 4))then
 
 
 
            ISR_Addr         <= INT_VECTOR_4;
 
 
 
            Pending(4)       <= '0';
 
 
 
            History(Hst_Ptr+1) <= 4;
 
 
 
            Hst_Ptr          <= Hst_Ptr + 1;
 
 
 
            Wait_for_FSM     <= '1';
 
 
 
          elsif(Pending(5) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 5))then
 
 
 
            ISR_Addr         <= INT_VECTOR_5;
 
 
 
            Pending(5)       <= '0';
 
 
 
            History(Hst_Ptr+1) <= 5;
 
 
 
            Hst_Ptr          <= Hst_Ptr + 1;
 
 
 
            Wait_for_FSM     <= '1';
 
 
 
          elsif(Pending(6) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 6))then
 
 
 
            ISR_Addr         <= INT_VECTOR_6;
 
 
 
            Pending(6)       <= '0';
 
 
 
            History(Hst_Ptr+1) <= 6;
 
 
 
            Hst_Ptr          <= Hst_Ptr + 1;
 
 
 
            Wait_for_FSM     <= '1';
 
 
 
          elsif(Pending(7) = '1' and (Hst_Ptr = 0 or History(Hst_Ptr) > 7))then
 
 
 
            ISR_Addr         <= INT_VECTOR_7;
 
 
 
            Pending(7)       <= '0';
 
 
 
            History(Hst_Ptr+1) <= 7;
 
 
 
            Hst_Ptr          <= Hst_Ptr + 1;
 
 
 
            Wait_for_FSM     <= '1';
 
 
 
          end if;
 
 
 
        end if;
 
 
 
 
 
 
 
        -- Reset the Wait_for_FSM flag on Int_Ack
 
 
 
        Ack_Q                <= Ack_D;
 
 
 
        Ack_Q1               <= Ack_Q;
 
 
 
        Int_Ack              <= Ack_Q1;
 
 
 
        if( Int_Ack = '1' )then
 
 
 
          Wait_for_FSM       <= '0';
 
 
 
        end if;
 
 
 
 
 
 
 
        Int_Req              <= Wait_for_FSM and (not Int_Ack);
 
 
 
 
 
 
 
        Int_RTI              <= Int_RTI_D;
 
 
 
        if( Int_RTI = '1' and Hst_Ptr > 0 )then
 
 
 
          Hst_Ptr           <= Hst_Ptr - 1;
 
 
 
        end if;
 
 
 
 
 
 
 
        -- Incr_ISR allows the CPU Core to advance the vector address to pop the
 
 
 
        --  lower half of the address.
 
 
 
        if( INT_Ctrl.Incr_ISR = '1' )then
 
 
 
          ISR_Addr           <= ISR_Addr + 1;
 
 
 
        end if;
 
 
 
 
 
 
 
-------------------------------------------------------------------------------
 
 
 
-- ALU (Arithmetic / Logic Unit)
 
 
 
-------------------------------------------------------------------------------
 
 
 
        Temp                 := (others => '0');
 
 
 
        Index                := conv_integer(ALU_Ctrl.Reg);
 
 
 
 
 
 
 
        case ALU_Ctrl.Oper is
 
 
 
          when ALU_INC | ALU_UPP => -- Rn = Rn + 1 : Flags N,C,Z
 
 
 
            Sum              := ("0" & x"01") +
 
 
 
                                ("0" & Regfile(Index));
 
 
 
            Flags(FL_CARRY)  <= Sum(8);
 
 
 
            Regfile(Index)   <= Sum(7 downto 0);
 
 
 
           -- ALU_INC and ALU_UPP are essentially the same, except that ALU_UPP
 
 
 
           --  doesn't set the N or Z flags. Note that the MSB can be used to
 
 
 
           --  distinguish between the two ALU modes.
 
 
 
           if( ALU_Ctrl.Oper(4) = '0' )then
 
 
 
             Flags(FL_ZERO)  <= '0';
 
 
 
             if( Sum(7 downto 0) = 0 )then
 
 
 
               Flags(FL_ZERO)<= '1';
 
 
 
             end if;
 
 
 
             Flags(FL_NEG)   <= Sum(7);
 
 
 
           end if;
 
 
 
 
 
 
 
          when ALU_UPP2 => -- Rn = Rn + C
 
 
 
            Sum              := ("0" & x"00") +
 
 
 
                                ("0" & Regfile(Index)) +
 
 
 
                                Flags(FL_CARRY);
 
 
 
            Flags(FL_CARRY)  <= Sum(8);
 
 
 
            Regfile(Index)   <= Sum(7 downto 0);
 
 
 
 
 
 
 
          when ALU_ADC => -- R0 = R0 + Rn + C : Flags N,C,Z
 
 
 
            Sum              := ("0" & Regfile(0)) +
 
 
 
                                ("0" & Regfile(Index)) +
 
 
 
                                Flags(FL_CARRY);
 
 
 
            Flags(FL_ZERO)   <= '0';
 
 
 
            if( Sum(7 downto 0) = 0 )then
 
 
 
              Flags(FL_ZERO) <= '1';
 
 
 
            end if;
 
 
 
            Flags(FL_CARRY)  <= Sum(8);
 
 
 
            Flags(FL_NEG)    <= Sum(7);
 
 
 
            Regfile(0)       <= Sum(7 downto 0);
 
 
 
 
 
 
 
          when ALU_TX0 => -- R0 = Rn : Flags N,Z
 
 
 
            Temp                 := "0" & Regfile(Index);
 
 
 
            Flags(FL_ZERO)   <= '0';
 
 
 
            if( Temp(7 downto 0) = 0 )then
 
 
 
              Flags(FL_ZERO) <= '1';
 
 
 
            end if;
 
 
 
            Flags(FL_NEG)    <= Temp(7);
 
 
 
            Regfile(0)       <= Temp(7 downto 0);
 
 
 
 
 
 
 
          when ALU_OR  => -- R0 = R0 | Rn : Flags N,Z
 
 
 
            Temp(7 downto 0) := Regfile(0) or Regfile(Index);
 
 
 
            Flags(FL_ZERO)   <= '0';
 
 
 
            if( Temp(7 downto 0) = 0 )then
 
 
 
              Flags(FL_ZERO) <= '1';
 
 
 
            end if;
 
 
 
            Flags(FL_NEG)    <= Temp(7);
 
 
 
            Regfile(0)       <= Temp(7 downto 0);
 
 
 
 
 
 
 
          when ALU_AND => -- R0 = R0 & Rn : Flags N,Z
 
 
 
            Temp(7 downto 0) := Regfile(0) and Regfile(Index);
 
 
 
            Flags(FL_ZERO)   <= '0';
 
 
 
            if( Temp(7 downto 0) = 0 )then
 
 
 
              Flags(FL_ZERO) <= '1';
 
 
 
            end if;
 
 
 
            Flags(FL_NEG)    <= Temp(7);
 
 
 
            Regfile(0)       <= Temp(7 downto 0);
 
 
 
 
 
 
 
          when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z
 
 
 
            Temp(7 downto 0) := Regfile(0) xor Regfile(Index);
 
 
 
            Flags(FL_ZERO)   <= '0';
 
 
 
            if( Temp(7 downto 0) = 0 )then
 
 
 
              Flags(FL_ZERO) <= '1';
 
 
 
            end if;
 
 
 
            Flags(FL_NEG)    <= Temp(7);
 
 
 
            Regfile(0)       <= Temp(7 downto 0);
 
 
 
 
 
 
 
          when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z
 
 
 
            Temp             := Regfile(Index) & Flags(FL_CARRY);
 
 
 
            Flags(FL_ZERO)   <= '0';
 
 
 
            if( Temp(7 downto 0) = 0 )then
 
 
 
              Flags(FL_ZERO) <= '1';
 
 
 
            end if;
 
 
 
            Flags(FL_CARRY)  <= Temp(8);
 
 
 
            Flags(FL_NEG)    <= Temp(7);
 
 
 
            Regfile(Index)   <= Temp(7 downto 0);
 
 
 
 
 
 
 
          when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z
 
 
 
            Temp             := Regfile(Index)(0) & Flags(FL_CARRY) &
 
 
 
                                Regfile(Index)(7 downto 1);
 
 
 
            Flags(FL_ZERO)   <= '0';
 
 
 
            if( Temp(7 downto 0) = 0 )then
 
 
 
              Flags(FL_ZERO) <= '1';
 
 
 
            end if;
 
 
 
            Flags(FL_CARRY)  <= Temp(8);
 
 
 
            Flags(FL_NEG)    <= Temp(7);
 
 
 
            Regfile(Index)   <= Temp(7 downto 0);
 
 
 
 
 
 
 
          when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
 
 
 
            Sum              := ("0" & Regfile(Index)) +
 
 
 
                                ("0" & x"FF");
 
 
 
            Flags(FL_ZERO)   <= '0';
 
 
 
            if( Sum(7 downto 0) = 0 )then
 
 
 
              Flags(FL_ZERO) <= '1';
 
 
 
            end if;
 
 
 
            Flags(FL_CARRY)  <= Sum(8);
 
 
 
            Flags(FL_NEG)    <= Sum(7);
 
 
 
            Regfile(Index)   <= Sum(7 downto 0);
 
 
 
 
 
 
 
          when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
 
 
 
            Sum              := ("0" & Regfile(0)) +
 
 
 
                                ("0" & (not Regfile(Index))) +
 
 
 
                                Flags(FL_CARRY);
 
 
 
            Flags(FL_ZERO)   <= '0';
 
 
 
            if( Sum(7 downto 0) = 0 )then
 
 
 
              Flags(FL_ZERO) <= '1';
 
 
 
            end if;
 
 
 
            Flags(FL_CARRY)  <= Sum(8);
 
 
 
            Flags(FL_NEG)    <= Sum(7);
 
 
 
            Regfile(0)       <= Sum(7 downto 0);
 
 
 
 
 
 
 
          when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z
 
 
 
            Sum              := ("0" & Regfile(0)) +
 
 
 
                                ("0" & Regfile(Index));
 
 
 
            Flags(FL_CARRY)  <= Sum(8);
 
 
 
            Regfile(0)       <= Sum(7 downto 0);
 
 
 
            Flags(FL_ZERO)   <= '0';
 
 
 
            if( Sum(7 downto 0) = 0 )then
 
 
 
              Flags(FL_ZERO) <= '1';
 
 
 
            end if;
 
 
 
            Flags(FL_NEG)    <= Sum(7);
 
 
 
 
 
 
 
          when ALU_STP => -- Sets bit(n) in the Flags register
 
 
 
            Flags(Index)     <= '1';
 
 
 
 
 
 
 
          when ALU_BTT => -- Z = !R0(N), N = R0(7)
 
 
 
            Flags(FL_ZERO)   <= not Regfile(0)(Index);
 
 
 
            Flags(FL_NEG)    <= Regfile(0)(7);
 
 
 
 
 
 
 
          when ALU_CLP => -- Clears bit(n) in the Flags register
 
 
 
            Flags(Index)     <= '0';
 
 
 
 
 
 
 
          when ALU_T0X => -- Rn = R0 : Flags N,Z
 
 
 
            Temp             := "0" & Regfile(0);
 
 
 
            Flags(FL_ZERO)   <= '0';
 
 
 
            if( Temp(7 downto 0) = 0 )then
 
 
 
              Flags(FL_ZERO) <= '1';
 
 
 
            end if;
 
 
 
            Flags(FL_NEG)    <= Temp(7);
 
 
 
            Regfile(Index)   <= Temp(7 downto 0);
 
 
 
 
 
 
 
          when ALU_CMP => -- Sets Flags on R0 - Rn : Flags N,C,Z
 
 
 
            Sum              := ("0" & Regfile(0)) +
 
 
 
                                ("0" & (not Regfile(Index))) +
 
 
 
                                '1';
 
 
 
            Flags(FL_ZERO)   <= '0';
 
 
 
            if( Sum(7 downto 0) = 0 )then
 
 
 
              Flags(FL_ZERO) <= '1';
 
 
 
            end if;
 
 
 
            Flags(FL_CARRY)  <= Sum(8);
 
 
 
            Flags(FL_NEG)    <= Sum(7);
 
 
 
 
 
 
 
          when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
 
 
 
            Regfile(0)       <= Mult(7 downto 0);
 
 
 
            Regfile(1)       <= Mult(15 downto 8);
 
 
 
            Flags(FL_ZERO)   <= '0';
 
 
 
            if( Mult = 0 )then
 
 
 
              Flags(FL_ZERO) <= '1';
 
 
 
            end if;
 
 
 
 
 
 
 
          when ALU_LDI | ALU_POP => -- Rn <= Data : Flags N,Z
 
 
 
            -- The POP instruction doesn't alter the flags, so we need to check
 
 
 
            if( ALU_Ctrl.Oper = ALU_LDI )then
 
 
 
              Flags(FL_ZERO) <= '0';
 
 
 
              if( ALU_Ctrl.Data = 0 )then
 
 
 
                Flags(FL_ZERO) <= '1';
 
 
 
              end if;
 
 
 
              Flags(FL_NEG)  <= ALU_Ctrl.Data(7);
 
 
 
            end if;
 
 
 
            Regfile(Index)   <= ALU_Ctrl.Data;
 
 
 
 
 
 
 
          when ALU_LDX => -- R0 <= Data : Flags N,Z
 
 
 
            Flags(FL_ZERO)   <= '0';
 
 
 
            if( ALU_Ctrl.Data = 0 )then
 
 
 
              Flags(FL_ZERO) <= '1';
 
 
 
            end if;
 
 
 
            Flags(FL_NEG)    <= ALU_Ctrl.Data(7);
 
 
 
            Regfile(0)       <= ALU_Ctrl.Data;
 
 
 
 
 
 
 
          when ALU_RFLG =>
 
 
 
            Flags            <= ALU_Ctrl.Data;
 
 
 
 
 
 
 
          when others =>
 
 
 
            null;
 
 
 
        end case;
 
 
 
 
 
 
 
      end if;
 
 
 
    end if;
 
    end if;
 
  end process;
 
  end process;
 
 
 
 
 
end architecture;
 
end architecture;
 
 
 
 
 
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