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https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_cpu.vhd] - Diff between revs 167 and 168
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| Rev 167 |
Rev 168 |
| Line 322... |
Line 322... |
PC_BRANCH, PC_LOAD );
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PC_BRANCH, PC_LOAD );
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type SP_MODES is ( SP_IDLE, SP_RSET, SP_POP, SP_PUSH );
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type SP_MODES is ( SP_IDLE, SP_RSET, SP_POP, SP_PUSH );
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type DP_MODES is ( DATA_BUS_IDLE, DATA_RD_MEM,
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type DP_MODES is ( DATA_BUS_IDLE, DATA_RD_MEM,
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DATA_WR_REG, DATA_WR_FLAG, DATA_WR_PC );
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DATA_WR_REG, DATA_WR_FLAG,
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DATA_WR_PC_LOWER, DATA_WR_PC_UPPER );
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type DP_CTRL_TYPE is record
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type DP_CTRL_TYPE is record
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Src : DP_MODES;
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Src : DP_MODES;
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Reg : SUBOP_TYPE;
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Reg : SUBOP_TYPE;
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end record;
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end record;
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| Line 416... |
Line 417... |
elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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IC := CACHE_IDLE;
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IC := CACHE_IDLE;
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SP := SP_IDLE;
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SP := SP_IDLE;
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DP.Src := DATA_RD_MEM;
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DP.Src := DATA_RD_MEM;
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DP.Reg := ACCUM;
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Ack_D := '0';
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Ack_D := '0';
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INT.Mask_Set := '0';
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INT.Mask_Set := '0';
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INT.Soft_Ints := x"00";
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INT.Soft_Ints := x"00";
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INT.Incr_ISR := '0';
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INT.Incr_ISR := '0';
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RegSel := conv_integer(CPU.SubOp_p0);
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RegSel := conv_integer(CPU.SubOp_p0);
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| Line 530... |
Line 530... |
CPU.State <= GMSK_C1;
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CPU.State <= GMSK_C1;
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when SOP_JSR =>
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when SOP_JSR =>
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IC := CACHE_OPER1;
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IC := CACHE_OPER1;
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PC := PC_IDLE;
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PC := PC_IDLE;
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DP.Src := DATA_WR_PC;
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DP.Src := DATA_WR_PC_UPPER;
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DP.Reg := ACCUM+1;
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CPU.State <= JSR_C1;
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CPU.State <= JSR_C1;
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when others => null;
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when others => null;
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end case;
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end case;
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| Line 856... |
Line 855... |
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when ISR_C3 =>
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when ISR_C3 =>
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IC := CACHE_OPER1;
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IC := CACHE_OPER1;
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PC := PC_IDLE;
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PC := PC_IDLE;
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SP := SP_PUSH;
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SP := SP_PUSH;
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DP.Src := DATA_WR_PC;
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DP.Src := DATA_WR_PC_UPPER;
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DP.Reg := ACCUM+1;
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Ack_D := '1';
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Ack_D := '1';
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CPU.A_Oper <= ALU_STP;
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CPU.A_Oper <= ALU_STP;
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CPU.A_Reg <= INT_FLAG;
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CPU.A_Reg <= INT_FLAG;
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CPU.State <= JSR_C1;
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CPU.State <= JSR_C1;
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when JSR_C1 =>
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when JSR_C1 =>
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IC := CACHE_OPER2;
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IC := CACHE_OPER2;
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PC := PC_IDLE;
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PC := PC_IDLE;
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SP := SP_PUSH;
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SP := SP_PUSH;
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DP.Src := DATA_WR_PC;
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DP.Src := DATA_WR_PC_LOWER;
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DP.Reg := ACCUM;
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CPU.State <= JSR_C2;
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CPU.State <= JSR_C2;
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when JSR_C2 =>
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when JSR_C2 =>
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SP := SP_PUSH;
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SP := SP_PUSH;
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PC := PC_LOAD;
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PC := PC_LOAD;
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| Line 1254... |
Line 1251... |
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when DATA_WR_FLAG =>
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when DATA_WR_FLAG =>
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Wr_Enable <= '1';
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Wr_Enable <= '1';
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Wr_Data <= Flags;
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Wr_Data <= Flags;
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when DATA_WR_PC =>
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when DATA_WR_PC_LOWER =>
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Wr_Enable <= '1';
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Wr_Enable <= '1';
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Wr_Data <= CPU.Program_Ctr(15 downto 8);
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if( DP.Reg = ACCUM )then
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Wr_Data <= CPU.Program_Ctr(7 downto 0);
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Wr_Data <= CPU.Program_Ctr(7 downto 0);
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end if;
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when DATA_WR_PC_UPPER =>
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Wr_Enable <= '1';
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Wr_Data <= CPU.Program_Ctr(15 downto 8);
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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