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-- Copyright (c)2006,2013 Jeremy Seth Henry
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-- Copyright (c)2006,2011,2012,2013,2015 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- Description: VHDL model of a RISC 8-bit processor core loosely based on the
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-- Description: VHDL model of a RISC 8-bit processor core loosely based on the
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-- : V8/ARC uRISC instruction set. Requires Open8_pkg.vhd
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-- : V8/ARC uRISC instruction set. Requires Open8_pkg.vhd
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-- :
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-- :
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-- Notes : Generic definitions
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-- Notes : Generic definitions
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-- :
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-- :
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-- : Program_Start_Addr - Determines the initial value of the
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-- : Program_Start_Addr sets the initial value of the program
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-- : program counter.
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-- : counter.
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-- :
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-- :
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-- : ISR_Start_Addr - determines the location of the interrupt
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-- : ISR_Start_Addr sets the location of the interrupt service
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-- : service vector table. There are 8 service vectors, or 16
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-- : vector table. There are 8 service vectors, or 16 bytes, which
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-- : bytes, which must be allocated to either ROM or RAM.
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-- : must be allocated to either ROM or RAM.
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-- :
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-- :
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-- : Stack_Start_Address - determines the initial (reset) value of
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-- : Stack_Start_Address sets the initial (reset) value of the
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-- : the stack pointer. Also used for the RSP instruction if
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-- : stack pointer. Also used for the RSP instruction if
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-- : Allow_Stack_Address_Move is 0.
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-- : Allow_Stack_Address_Move is false.
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-- :
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-- :
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-- : Allow_Stack_Address_Move - When set to 1, allows the RSP to be
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-- : Allow_Stack_Address_Move, when set true, allows the RSP to be
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-- : programmed via thet RSP instruction. If enabled, the contents
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-- : programmed via thet RSP instruction. If enabled, the contents
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-- : of R1:R0 are used to initialize the stack pointer.
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-- : of R1:R0 are used to initialize the stack pointer.
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-- :
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-- :
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-- : The Enable_Auto_Increment generic can be used to modify the
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-- : The Enable_Auto_Increment generic can be used to modify the
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-- : indexed instructions such that specifying an odd register
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-- : indexed instructions such that specifying an odd register
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-- : triggers the wait for interrupt state, but without triggering
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-- : triggers the wait for interrupt state, but without triggering
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-- : a soft interrupt in lieu of its normal behavior, which is to
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-- : a soft interrupt in lieu of its normal behavior, which is to
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-- : insert several dead clock cycles - essentially a long NOP
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-- : insert several dead clock cycles - essentially a long NOP
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-- :
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-- :
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-- : Enable_NMI overrides the mask bit for interrupt 0, creating a
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-- : Enable_NMI overrides the mask bit for interrupt 0, creating a
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-- : non-maskable interrupt at the highest priority.
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-- : non-maskable interrupt at the highest priority. To remain
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-- : true to the original core, this should be set false.
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-- :
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-- :
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-- : Default_Interrupt_Mask - Determines the intial value of the
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-- : Default_Interrupt_Mask sets the intial/reset value of the
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-- : interrupt mask. To remain true to the original core, which
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-- : interrupt mask. To remain true to the original core, which
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-- : had no interrupt mask, this should be set to x"FF". Otherwise
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-- : had no interrupt mask, this should be set to x"FF". Otherwise
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-- : it can be initialized to any value. Enable_NMI will logically
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-- : it can be initialized to any value. Note that Enable_NMI
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-- : force the LSB high.
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-- : will logically force the LSB high.
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-- :
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-- :
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-- : Reset_Level - Determines whether the processor registers reset
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-- : Reset_Level determines whether the processor registers reset
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-- : on a high or low level from higher logic.
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-- : on a high or low level from higher logic.
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-- :
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-- :
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-- : Architecture notes
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-- : Architecture notes
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-- : This model deviates from the original ISA in a few important
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-- : This model deviates from the original ISA in a few important
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-- : ways.
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-- : ways.
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-- : allow the stack pointer to be sourced from R1:R0.
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-- : allow the stack pointer to be sourced from R1:R0.
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-- :
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-- :
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-- : Sixth, the BRK instruction can optionally implement a WAI,
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-- : Sixth, the BRK instruction can optionally implement a WAI,
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-- : which is the same as the INT instruction without the soft
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-- : which is the same as the INT instruction without the soft
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-- : interrupt, as a way to put the processor to "sleep" until the
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-- : interrupt, as a way to put the processor to "sleep" until the
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-- : next interrupt.
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-- : next external interrupt.
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-- :
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-- :
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-- : Seventh, the original CPU model had 8 non-maskable interrupts
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-- : Seventh, the original CPU model had 8 non-maskable interrupts
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-- : with priority. This model has the same 8 interrupts, but
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-- : with priority. This model has the same 8 interrupts, but
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-- : allows software to mask them (with an additional option to
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-- : allows software to mask them (with an additional option to
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-- : override the highest priority interrupt, making it the NMI.)
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-- : override the highest priority interrupt, making it the NMI.)
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-- : The interrupt code will retain memory of lower priority
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-- : interrupts, and execute them as it can.
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-- :
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-- :
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-- : Lastly, previous unmapped instructions in the OP_STK opcode
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-- : Lastly, previous unmapped instructions in the OP_STK opcode
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-- : were repurposed to support a new interrupt mask.
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-- : were repurposed to support a new interrupt mask.
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-- : SMSK and GMSK transfer the contents of R0 (accumulator)
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-- : SMSK and GMSK transfer the contents of R0 (accumulator)
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-- : to/from the interrupt mask register. SMSK is immediate, while
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-- : to/from the interrupt mask register. SMSK is immediate, while
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-- : GMSK has the same overhead as a math instruction.
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-- : GMSK has the same overhead as a math instruction.
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--
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-- Revision History
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 07/19/06 Design Start
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-- Seth Henry 01/18/11 Fixed BTT instruction to match V8
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-- Seth Henry 07/22/11 Fixed interrupt transition logic to avoid data
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-- corruption issues.
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-- Seth Henry 07/26/11 Optimized logic in ALU, stack pointer, and data
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-- path sections.
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-- Seth Henry 07/27/11 Optimized logic for timing, merged blocks into
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-- single entity.
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-- Seth Henry 09/20/11 Added BRK_Implements_WAI option, allowing the
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-- processor to wait for an interrupt instead of the
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-- normal BRK behavior.
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-- Seth Henry 12/20/11 Modified core to allow WAIT_FOR_INT state to idle
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-- the bus entirely (Rd_Enable is low)
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-- Seth Henry 02/03/12 Replaced complex interrupt controller with simpler,
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-- faster logic that simply does priority encoding.
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-- Seth Henry 08/06/13 Removed HALT functionality
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-- Seth Henry 10/29/15 Fixed inverted carry logic in CMP and SBC instrs
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
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library work;
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library work;
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use work.Open8_pkg.all;
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use work.Open8_pkg.all;
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entity Open8_CPU is
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entity Open8_CPU is
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generic(
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generic(
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Program_Start_Addr : ADDRESS_TYPE := x"0090"; -- Initial PC location
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Program_Start_Addr : ADDRESS_TYPE := x"0000"; -- Initial PC location
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ISR_Start_Addr : ADDRESS_TYPE := x"0080"; -- Bottom of ISR vec's
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ISR_Start_Addr : ADDRESS_TYPE := x"FFF0"; -- Bottom of ISR vec's
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Stack_Start_Addr : ADDRESS_TYPE := x"007F"; -- Top of Stack
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Stack_Start_Addr : ADDRESS_TYPE := x"03FF"; -- Top of Stack
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Allow_Stack_Address_Move : boolean := false; -- Use Normal v8 RSP
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Allow_Stack_Address_Move : boolean := false; -- Use Normal v8 RSP
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Enable_Auto_Increment : boolean := false; -- Modify indexed instr
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Enable_Auto_Increment : boolean := false; -- Modify indexed instr
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BRK_Implements_WAI : boolean := false; -- BRK -> Wait for Int
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BRK_Implements_WAI : boolean := false; -- BRK -> Wait for Int
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Enable_NMI : boolean := true; -- force mask for int 0
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Enable_NMI : boolean := true; -- Force INTR0 enabled
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Default_Interrupt_Mask : DATA_TYPE := x"FF"; -- Enable all Ints
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Default_Interrupt_Mask : DATA_TYPE := x"FF"; -- Enable all Ints
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Reset_Level : std_logic := '0' ); -- Active reset level
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Reset_Level : std_logic := '0' ); -- Active reset level
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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Wr_Enable : out std_logic );
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Wr_Enable : out std_logic );
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end entity;
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end entity;
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architecture behave of Open8_CPU is
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architecture behave of Open8_CPU is
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subtype OPCODE_TYPE is std_logic_vector(4 downto 0);
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constant INT_VECTOR_0 : ADDRESS_TYPE := ISR_Start_Addr;
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subtype SUBOP_TYPE is std_logic_vector(2 downto 0);
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-- All opcodes should be identical to the opcode used by the assembler
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-- In this case, they match the original V8/ARC uRISC ISA
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constant OP_INC : OPCODE_TYPE := "00000";
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constant OP_ADC : OPCODE_TYPE := "00001";
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constant OP_TX0 : OPCODE_TYPE := "00010";
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constant OP_OR : OPCODE_TYPE := "00011";
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constant OP_AND : OPCODE_TYPE := "00100";
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constant OP_XOR : OPCODE_TYPE := "00101";
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constant OP_ROL : OPCODE_TYPE := "00110";
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constant OP_ROR : OPCODE_TYPE := "00111";
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constant OP_DEC : OPCODE_TYPE := "01000";
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constant OP_SBC : OPCODE_TYPE := "01001";
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constant OP_ADD : OPCODE_TYPE := "01010";
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constant OP_STP : OPCODE_TYPE := "01011";
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constant OP_BTT : OPCODE_TYPE := "01100";
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constant OP_CLP : OPCODE_TYPE := "01101";
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constant OP_T0X : OPCODE_TYPE := "01110";
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constant OP_CMP : OPCODE_TYPE := "01111";
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constant OP_PSH : OPCODE_TYPE := "10000";
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constant OP_POP : OPCODE_TYPE := "10001";
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constant OP_BR0 : OPCODE_TYPE := "10010";
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constant OP_BR1 : OPCODE_TYPE := "10011";
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constant OP_DBNZ : OPCODE_TYPE := "10100";
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constant OP_INT : OPCODE_TYPE := "10101";
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constant OP_MUL : OPCODE_TYPE := "10110";
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constant OP_STK : OPCODE_TYPE := "10111";
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constant OP_UPP : OPCODE_TYPE := "11000";
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constant OP_STA : OPCODE_TYPE := "11001";
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constant OP_STX : OPCODE_TYPE := "11010";
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constant OP_STO : OPCODE_TYPE := "11011";
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constant OP_LDI : OPCODE_TYPE := "11100";
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constant OP_LDA : OPCODE_TYPE := "11101";
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constant OP_LDX : OPCODE_TYPE := "11110";
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constant OP_LDO : OPCODE_TYPE := "11111";
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-- OP_STK uses the lower 3 bits to further refine the instruction by
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-- repurposing the source register field. These "sub opcodes" are
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-- take the place of the register select for the OP_STK opcode
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constant SOP_RSP : SUBOP_TYPE := "000";
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constant SOP_RTS : SUBOP_TYPE := "001";
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constant SOP_RTI : SUBOP_TYPE := "010";
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constant SOP_BRK : SUBOP_TYPE := "011";
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constant SOP_JMP : SUBOP_TYPE := "100";
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constant SOP_SMSK : SUBOP_TYPE := "101";
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constant SOP_GMSK : SUBOP_TYPE := "110";
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constant SOP_JSR : SUBOP_TYPE := "111";
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type CPU_STATES is (
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-- Instruction fetch & Decode
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PIPE_FILL_0, PIPE_FILL_1, PIPE_FILL_2, INSTR_DECODE,
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-- Branching
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BRN_C1, DBNZ_C1, DBNZ_C2, JMP_C1, JMP_C2,
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-- Loads
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LDA_C1, LDA_C2, LDA_C3, LDA_C4, LDI_C1,
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LDO_C1, LDX_C1, LDX_C2, LDX_C3, LDX_C4,
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-- Stores
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STA_C1, STA_C2, STO_C1, STO_C2, STX_C1, STX_C2,
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-- math
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MATH_C1, GMSK_C1, MUL_C1, UPP_C1,
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-- Stack
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PSH_C1, POP_C1, POP_C2, POP_C3, POP_C4,
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-- Subroutines & Interrupts
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WAIT_FOR_INT, ISR_C1, ISR_C2, ISR_C3, JSR_C1, JSR_C2,
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RTS_C1, RTS_C2, RTS_C3, RTS_C4, RTS_C5, RTI_C6,
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-- Debugging
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BRK_C1 );
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-- To simplify the logic, the first 16 of these should exactly match their
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-- corresponding Opcodes. This allows the state logic to simply pass the
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-- opcode field to the ALU for most math operations.
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constant ALU_INC : OPCODE_TYPE := "00000"; -- x"00"
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constant ALU_UPP1 : OPCODE_TYPE := "00000"; -- Alias of ALU_INC
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constant ALU_ADC : OPCODE_TYPE := "00001"; -- x"01"
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constant ALU_TX0 : OPCODE_TYPE := "00010"; -- x"02"
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constant ALU_OR : OPCODE_TYPE := "00011"; -- x"03"
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constant ALU_AND : OPCODE_TYPE := "00100"; -- x"04"
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constant ALU_XOR : OPCODE_TYPE := "00101"; -- x"05"
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constant ALU_ROL : OPCODE_TYPE := "00110"; -- x"06"
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constant ALU_ROR : OPCODE_TYPE := "00111"; -- x"07"
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constant ALU_DEC : OPCODE_TYPE := "01000"; -- x"08"
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constant ALU_SBC : OPCODE_TYPE := "01001"; -- x"09"
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constant ALU_ADD : OPCODE_TYPE := "01010"; -- x"0A"
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constant ALU_STP : OPCODE_TYPE := "01011"; -- x"0B"
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constant ALU_BTT : OPCODE_TYPE := "01100"; -- x"0C"
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constant ALU_CLP : OPCODE_TYPE := "01101"; -- x"0D"
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constant ALU_T0X : OPCODE_TYPE := "01110"; -- x"0E"
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constant ALU_CMP : OPCODE_TYPE := "01111"; -- x"0F"
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constant ALU_IDLE : OPCODE_TYPE := "10000"; -- x"10"
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constant ALU_UPP2 : OPCODE_TYPE := "10010"; -- x"11"
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constant ALU_RFLG : OPCODE_TYPE := "10011"; -- x"12"
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constant ALU_MUL : OPCODE_TYPE := "10110"; -- x"16"
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constant ALU_LDI : OPCODE_TYPE := "11100"; -- x"1C"
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constant FL_ZERO : integer := 0;
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constant FL_CARRY : integer := 1;
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constant FL_NEG : integer := 2;
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constant FL_INT_EN : integer := 3;
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constant FL_GP1 : integer := 4;
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constant FL_GP2 : integer := 5;
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constant FL_GP3 : integer := 6;
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constant FL_GP4 : integer := 7;
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constant ACCUM : SUBOP_TYPE := "000";
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constant INT_FLAG : SUBOP_TYPE := "011";
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type REGFILE_TYPE is array (0 to 7) of DATA_TYPE;
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subtype FLAG_TYPE is DATA_TYPE;
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constant INT_VECTOR_0 : ADDRESS_TYPE := ISR_Start_Addr + 0;
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constant INT_VECTOR_1 : ADDRESS_TYPE := ISR_Start_Addr + 2;
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constant INT_VECTOR_1 : ADDRESS_TYPE := ISR_Start_Addr + 2;
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constant INT_VECTOR_2 : ADDRESS_TYPE := ISR_Start_Addr + 4;
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constant INT_VECTOR_2 : ADDRESS_TYPE := ISR_Start_Addr + 4;
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constant INT_VECTOR_3 : ADDRESS_TYPE := ISR_Start_Addr + 6;
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constant INT_VECTOR_3 : ADDRESS_TYPE := ISR_Start_Addr + 6;
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constant INT_VECTOR_4 : ADDRESS_TYPE := ISR_Start_Addr + 8;
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constant INT_VECTOR_4 : ADDRESS_TYPE := ISR_Start_Addr + 8;
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constant INT_VECTOR_5 : ADDRESS_TYPE := ISR_Start_Addr + 10;
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constant INT_VECTOR_5 : ADDRESS_TYPE := ISR_Start_Addr + 10;
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constant INT_VECTOR_6 : ADDRESS_TYPE := ISR_Start_Addr + 12;
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constant INT_VECTOR_6 : ADDRESS_TYPE := ISR_Start_Addr + 12;
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constant INT_VECTOR_7 : ADDRESS_TYPE := ISR_Start_Addr + 14;
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constant INT_VECTOR_7 : ADDRESS_TYPE := ISR_Start_Addr + 14;
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type CPU_CTRL_TYPE is record
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signal Halt : std_logic;
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State : CPU_STATES;
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LS_Address : ADDRESS_TYPE;
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Program_Ctr : ADDRESS_TYPE;
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Stack_Ptr : ADDRESS_TYPE;
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Opcode : OPCODE_TYPE;
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SubOp_p0 : SUBOP_TYPE;
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SubOp_p1 : SUBOP_TYPE;
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Cache_Valid : std_logic;
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Prefetch : DATA_TYPE;
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Operand1 : DATA_TYPE;
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Operand2 : DATA_TYPE;
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AutoIncr : std_logic;
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A_Oper : OPCODE_TYPE;
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A_Reg : SUBOP_TYPE;
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A_Data : DATA_TYPE;
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A_NoFlags : std_logic;
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M_Reg : SUBOP_TYPE;
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M_Prod : ADDRESS_TYPE;
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Regfile : REGFILE_TYPE;
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Flags : FLAG_TYPE;
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Int_Mask : DATA_TYPE;
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Int_Addr : ADDRESS_TYPE;
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Int_Pending : DATA_TYPE;
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Int_Level : integer range 0 to 7;
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Wait_for_FSM : std_logic;
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end record;
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signal CPU : CPU_CTRL_TYPE;
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alias Accumulator is CPU.Regfile(0);
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alias Flags is CPU.Flags;
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signal Ack_Q, Ack_Q1 : std_logic;
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signal Int_Req, Int_Ack : std_logic;
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type IC_MODES is ( CACHE_IDLE, CACHE_INSTR, CACHE_OPER1, CACHE_OPER2,
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CACHE_PREFETCH, CACHE_PFFLUSH, CACHE_INVALIDATE );
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type PC_MODES is ( PC_INCR, PC_IDLE, PC_REV1, PC_REV2, PC_REV3,
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PC_BRANCH, PC_LOAD );
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type SP_MODES is ( SP_IDLE, SP_RSET, SP_POP, SP_PUSH );
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type DP_MODES is ( DATA_BUS_IDLE, DATA_RD_MEM,
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DATA_WR_REG, DATA_WR_FLAG,
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DATA_WR_PC_LOWER, DATA_WR_PC_UPPER );
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type DP_CTRL_TYPE is record
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Src : DP_MODES;
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Reg : SUBOP_TYPE;
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end record;
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type INT_CTRL_TYPE is record
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Mask_Set : std_logic;
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Soft_Ints : INTERRUPT_BUNDLE;
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Incr_ISR : std_logic;
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end record;
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begin
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signal CPU_Next_State : CPU_STATES := PIPE_FILL_0;
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signal CPU_State : CPU_STATES := PIPE_FILL_0;
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Address_Sel: process( CPU )
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signal Cache_Ctrl : CACHE_MODES := CACHE_IDLE;
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variable Offset_SX : ADDRESS_TYPE;
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begin
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Offset_SX(15 downto 8) := (others => CPU.Operand1(7));
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Offset_SX(7 downto 0) := CPU.Operand1;
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case( CPU.State )is
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signal Opcode : OPCODE_TYPE := (others => '0');
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when LDO_C1 | LDX_C1 | STO_C1 | STX_C1 =>
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signal SubOp, SubOp_p1 : SUBOP_TYPE := (others => '0');
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Address <= CPU.LS_Address + Offset_SX;
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when LDA_C2 | STA_C2 =>
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Address <= (CPU.Operand2 & CPU.Operand1);
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when PSH_C1 | POP_C1 | ISR_C3 | JSR_C1 | JSR_C2 |
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RTS_C1 | RTS_C2 | RTS_C3 =>
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Address <= CPU.Stack_Ptr;
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when ISR_C1 | ISR_C2 =>
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Address <= CPU.Int_Addr;
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when others =>
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Address <= CPU.Program_Ctr;
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end case;
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end process;
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CPU_Proc: process( Clock, Reset )
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signal Prefetch : DATA_TYPE := x"00";
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variable IC : IC_MODES;
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signal Operand1, Operand2 : DATA_TYPE := x"00";
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variable PC : PC_MODES;
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variable SP : SP_MODES;
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variable DP : DP_CTRL_TYPE;
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variable INT : INT_CTRL_TYPE;
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variable RegSel : integer range 0 to 7;
|
|
variable Reg_l, Reg_u : integer range 0 to 7;
|
|
variable Ack_D : std_logic;
|
|
variable Offset_SX : ADDRESS_TYPE;
|
|
variable Index : integer range 0 to 7;
|
|
variable Temp : std_logic_vector(8 downto 0);
|
|
begin
|
|
if( Reset = Reset_Level )then
|
|
CPU.State <= PIPE_FILL_0;
|
|
CPU.LS_Address <= (others => '0');
|
|
CPU.Program_Ctr <= Program_Start_Addr;
|
|
CPU.Stack_Ptr <= Stack_Start_Addr;
|
|
CPU.Opcode <= (others => '0');
|
|
CPU.SubOp_p0 <= (others => '0');
|
|
CPU.SubOp_p1 <= (others => '0');
|
|
CPU.Prefetch <= (others => '0');
|
|
CPU.Operand1 <= (others => '0');
|
|
CPU.Operand2 <= (others => '0');
|
|
CPU.AutoIncr <= '0';
|
|
CPU.Cache_Valid <= '0';
|
|
CPU.A_Oper <= ALU_IDLE;
|
|
CPU.A_Reg <= ACCUM;
|
|
CPU.A_Data <= x"00";
|
|
CPU.A_NoFlags <= '0';
|
|
CPU.M_Reg <= (others => '0');
|
|
for i in 0 to 7 loop
|
|
CPU.Regfile(i) <= x"00";
|
|
end loop;
|
|
CPU.Flags <= (others => '0');
|
|
if( Enable_NMI )then
|
|
CPU.Int_Mask <= Default_Interrupt_Mask(7 downto 1) & '1';
|
|
else
|
|
CPU.Int_Mask <= Default_Interrupt_Mask;
|
|
end if;
|
|
CPU.Int_Addr <= (others => '0');
|
|
CPU.Int_Pending <= (others => '0');
|
|
CPU.Int_Level <= 7;
|
|
CPU.Wait_for_FSM <= '0';
|
|
|
|
Ack_Q <= '0';
|
signal Instr_Prefetch : std_logic := '0';
|
Ack_Q1 <= '0';
|
|
Int_Ack <= '0';
|
|
Int_Req <= '0';
|
|
|
|
Wr_Data <= x"00";
|
signal PC_Ctrl : PC_CTRL_TYPE;
|
Wr_Enable <= '0';
|
signal Program_Ctr : ADDRESS_TYPE := x"0000";
|
Rd_Enable <= '1';
|
|
elsif( rising_edge(Clock) )then
|
|
|
|
IC := CACHE_IDLE;
|
signal SP_Ctrl : SP_CTRL_TYPE;
|
SP := SP_IDLE;
|
signal Stack_Ptr : ADDRESS_TYPE := x"0000";
|
DP.Src := DATA_RD_MEM;
|
|
Ack_D := '0';
|
|
INT.Mask_Set := '0';
|
|
INT.Soft_Ints := x"00";
|
|
INT.Incr_ISR := '0';
|
|
RegSel := conv_integer(CPU.SubOp_p0);
|
|
|
|
if( Enable_Auto_Increment )then
|
signal DP_Ctrl : DATA_CTRL_TYPE;
|
Reg_l := conv_integer(CPU.SubOp_p0(2 downto 1) & '0');
|
|
Reg_u := conv_integer(CPU.SubOp_p0(2 downto 1) & '1');
|
|
else
|
|
Reg_l := conv_integer(CPU.SubOp_p0);
|
|
Reg_u := conv_integer(CPU.SubOp_p1);
|
|
end if;
|
|
|
|
CPU.LS_Address <= CPU.Regfile(Reg_u) & CPU.Regfile(Reg_l);
|
signal INT_Ctrl : INT_CTRL_TYPE;
|
|
signal Ack_D, Ack_Q, Ack_Q1: std_logic := '0';
|
|
signal Int_Req, Int_Ack : std_logic := '0';
|
|
signal Int_Mask : DATA_TYPE := x"00";
|
|
signal ISR_Addr : ADDRESS_TYPE := x"0000";
|
|
signal i_Ints : INTERRUPT_BUNDLE := x"00";
|
|
signal Pending : INTERRUPT_BUNDLE := x"00";
|
|
signal Wait_for_FSM : std_logic := '0';
|
|
|
CPU.AutoIncr <= '0';
|
signal ALU_Ctrl : ALU_CTRL_TYPE;
|
if( Enable_Auto_Increment )then
|
signal Regfile : REGFILE_TYPE;
|
CPU.AutoIncr <= CPU.SubOp_p0(0);
|
signal Flags : FLAG_TYPE;
|
end if;
|
signal Mult : ADDRESS_TYPE := x"0000";
|
|
|
|
begin
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- State Logic / Instruction Decoding & Execution
|
|
-- Combinatorial portion of CPU finite state machine
|
|
-------------------------------------------------------------------------------
|
|
|
CPU.A_Oper <= ALU_IDLE;
|
State_Logic: process(CPU_State, Regfile, Flags, Int_Mask, Opcode,
|
CPU.A_Reg <= ACCUM;
|
SubOp , SubOp_p1, Operand1, Operand2, Int_Req,
|
CPU.A_Data <= x"00";
|
Program_Ctr, Stack_Ptr, ISR_Addr )
|
CPU.A_NoFlags <= '0';
|
variable Reg, Reg_1 : integer range 0 to 7 := 0;
|
|
variable Offset_SX : ADDRESS_TYPE;
|
|
begin
|
|
CPU_Next_State <= CPU_State;
|
|
Cache_Ctrl <= CACHE_IDLE;
|
|
--
|
|
ALU_Ctrl.Oper <= ALU_IDLE;
|
|
ALU_Ctrl.Reg <= ACCUM;
|
|
ALU_Ctrl.Data <= x"00";
|
|
--
|
|
PC_Ctrl.Oper <= PC_IDLE;
|
|
PC_Ctrl.Offset <= x"03";
|
|
PC_Ctrl.Addr <= x"0000";
|
|
--
|
|
SP_Ctrl.Oper <= SP_IDLE;
|
|
--
|
|
Address <= Program_Ctr;
|
|
--
|
|
DP_Ctrl.Src <= DATA_RD_MEM;
|
|
DP_Ctrl.Reg <= ACCUM;
|
|
--
|
|
INT_Ctrl.Mask_Set <= '0';
|
|
INT_Ctrl.Soft_Ints <= x"00";
|
|
INT_Ctrl.Incr_ISR <= '0';
|
|
Ack_D <= '0';
|
|
|
|
-- Assign the most common value of Reg and Reg1 outside the case structure
|
|
-- to simplify things.
|
|
Reg := conv_integer(SubOp);
|
|
Reg_1 := conv_integer(SubOp_p1);
|
|
Offset_SX(15 downto 0) := (others => Operand1(7));
|
|
Offset_SX(7 downto 0) := Operand1;
|
|
|
case( CPU.State )is
|
case CPU_State is
|
|
-------------------------------------------------------------------------------
|
|
-- Initial Instruction fetch & decode
|
|
-------------------------------------------------------------------------------
|
when PIPE_FILL_0 =>
|
when PIPE_FILL_0 =>
|
PC := PC_INCR;
|
CPU_Next_State <= PIPE_FILL_1;
|
CPU.State <= PIPE_FILL_1;
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
when PIPE_FILL_1 =>
|
when PIPE_FILL_1 =>
|
PC := PC_INCR;
|
CPU_Next_State <= PIPE_FILL_2;
|
CPU.State <= PIPE_FILL_2;
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
when PIPE_FILL_2 =>
|
when PIPE_FILL_2 =>
|
IC := CACHE_INSTR;
|
CPU_Next_State <= INSTR_DECODE;
|
PC := PC_INCR;
|
Cache_Ctrl <= CACHE_INSTR;
|
CPU.State <= INSTR_DECODE;
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
-------------------------------------------------------------------------------
|
|
-- Instruction Decode and dispatch
|
|
-------------------------------------------------------------------------------
|
|
|
|
when INSTR_DECODE =>
|
when INSTR_DECODE =>
|
IC := CACHE_INSTR;
|
CPU_Next_State <= INSTR_DECODE;
|
PC := PC_INCR;
|
Cache_Ctrl <= CACHE_INSTR;
|
case CPU.Opcode is
|
|
|
case Opcode is
|
when OP_PSH =>
|
when OP_PSH =>
|
IC := CACHE_PREFETCH;
|
CPU_Next_State <= PSH_C1;
|
PC := PC_IDLE;
|
Cache_Ctrl <= CACHE_PREFETCH;
|
DP.Src := DATA_WR_REG;
|
PC_Ctrl.Oper <= PC_REV1;
|
DP.Reg := CPU.SubOp_p0;
|
DP_Ctrl.Src <= DATA_WR_REG;
|
CPU.State <= PSH_C1;
|
DP_Ctrl.Reg <= SubOp;
|
|
|
when OP_POP =>
|
when OP_POP =>
|
IC := CACHE_PREFETCH;
|
CPU_Next_State <= POP_C1;
|
PC := PC_REV2;
|
Cache_Ctrl <= CACHE_PREFETCH;
|
SP := SP_POP;
|
PC_Ctrl.Oper <= PC_REV2;
|
CPU.State <= POP_C1;
|
SP_Ctrl.Oper <= SP_POP;
|
|
|
when OP_BR0 | OP_BR1 =>
|
when OP_BR0 | OP_BR1 =>
|
IC := CACHE_OPER1;
|
CPU_Next_State <= BRN_C1;
|
CPU.State <= BRN_C1;
|
Cache_Ctrl <= CACHE_OPER1;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
when OP_DBNZ =>
|
when OP_DBNZ =>
|
IC := CACHE_OPER1;
|
CPU_Next_State <= DBNZ_C1;
|
CPU.A_Oper <= ALU_DEC;
|
Cache_Ctrl <= CACHE_OPER1;
|
CPU.A_Reg <= CPU.SubOp_p0;
|
PC_Ctrl.Oper <= PC_INCR;
|
CPU.A_Data <= CPU.Regfile(RegSel);
|
ALU_Ctrl.Oper <= ALU_DEC;
|
CPU.State <= DBNZ_C1;
|
ALU_Ctrl.Reg <= SubOp;
|
|
|
when OP_INT =>
|
when OP_INT =>
|
if( CPU.Int_Mask(RegSel) = '1' )then
|
PC_Ctrl.Oper <= PC_INCR;
|
CPU.State <= WAIT_FOR_INT;
|
-- Make sure the requested interrupt is actually enabled first
|
INT.Soft_Ints(RegSel) := '1';
|
if( Int_Mask(Reg) = '1' )then
|
|
CPU_Next_State <= WAIT_FOR_INT;
|
|
INT_Ctrl.Soft_Ints(Reg) <= '1';
|
end if;
|
end if;
|
|
|
when OP_STK =>
|
when OP_STK =>
|
case CPU.SubOp_p0 is
|
case SubOp is
|
when SOP_RSP =>
|
when SOP_RSP =>
|
SP := SP_RSET;
|
PC_Ctrl.Oper <= PC_INCR;
|
|
SP_Ctrl.Oper <= SP_RSET;
|
|
|
when SOP_RTS | SOP_RTI =>
|
when SOP_RTS | SOP_RTI =>
|
IC := CACHE_IDLE;
|
CPU_Next_State <= RTS_C1;
|
PC := PC_IDLE;
|
Cache_Ctrl <= CACHE_IDLE;
|
SP := SP_POP;
|
SP_Ctrl.Oper <= SP_POP;
|
CPU.State <= RTS_C1;
|
|
|
|
when SOP_BRK =>
|
when SOP_BRK =>
|
|
CPU_Next_State <= BRK_C1;
|
|
PC_Ctrl.Oper <= PC_REV2;
|
|
-- If Break implements Wait for Interrupt, replace the normal
|
|
-- flow with a modified version of the INT instruction
|
if( BRK_Implements_WAI )then
|
if( BRK_Implements_WAI )then
|
CPU.State<= WAIT_FOR_INT;
|
CPU_Next_State <= WAIT_FOR_INT;
|
else
|
PC_Ctrl.Oper <= PC_INCR;
|
PC := PC_REV2;
|
|
CPU.State<= BRK_C1;
|
|
end if;
|
end if;
|
|
|
when SOP_JMP =>
|
when SOP_JMP =>
|
IC := CACHE_OPER1;
|
CPU_Next_State <= JMP_C1;
|
PC := PC_IDLE;
|
Cache_Ctrl <= CACHE_OPER1;
|
CPU.State <= JMP_C1;
|
|
|
|
when SOP_SMSK =>
|
when SOP_SMSK =>
|
INT.Mask_Set := '1';
|
PC_Ctrl.Oper <= PC_INCR;
|
|
INT_Ctrl.Mask_Set <= '1';
|
|
|
when SOP_GMSK =>
|
when SOP_GMSK =>
|
IC := CACHE_PREFETCH;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC := PC_REV1;
|
ALU_Ctrl.Oper<= ALU_LDI;
|
CPU.State <= GMSK_C1;
|
ALU_Ctrl.Reg <= ACCUM;
|
|
ALU_Ctrl.Data<= Int_Mask;
|
|
|
when SOP_JSR =>
|
when SOP_JSR =>
|
IC := CACHE_OPER1;
|
CPU_Next_State <= JSR_C1;
|
PC := PC_IDLE;
|
Cache_Ctrl <= CACHE_OPER1;
|
DP.Src := DATA_WR_PC_UPPER;
|
DP_Ctrl.Src <= DATA_WR_PC;
|
CPU.State <= JSR_C1;
|
DP_Ctrl.Reg <= ACCUM+1;
|
|
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
|
|
when OP_MUL =>
|
when OP_MUL =>
|
IC := CACHE_PREFETCH;
|
CPU_Next_State <= MUL_C1;
|
PC := PC_REV1;
|
-- We need to back the PC up by 1, and allow it to refill. An
|
CPU.M_Reg <= CPU.SubOp_p0;
|
-- unfortunate consequence of the pipelining. We can get away with
|
CPU.State <= MUL_C1;
|
-- only 1 extra clock by pre-fetching the next instruction, though
|
|
Cache_Ctrl <= CACHE_PREFETCH;
|
|
PC_Ctrl.Oper <= PC_REV1;
|
|
-- Multiplication is automatic, but requires a single clock cycle.
|
|
-- We need to specify the register for Rn (R1:R0 = R0 * Rn) now,
|
|
-- but will issue the multiply command on the next clock to copy
|
|
-- the results to the specified register.
|
|
ALU_Ctrl.Oper <= ALU_IDLE;
|
|
ALU_Ctrl.Reg <= SubOp;
|
|
|
when OP_UPP =>
|
when OP_UPP =>
|
IC := CACHE_PREFETCH;
|
CPU_Next_State <= UPP_C1;
|
PC := PC_REV1;
|
Cache_Ctrl <= CACHE_PREFETCH;
|
CPU.A_Oper <= ALU_UPP1;
|
PC_Ctrl.Oper <= PC_REV1;
|
CPU.A_NoFlags <= '1';
|
ALU_Ctrl.Oper <= Opcode;
|
CPU.A_Reg <= CPU.SubOp_p0;
|
ALU_Ctrl.Reg <= SubOp;
|
CPU.A_Data <= CPU.Regfile(RegSel);
|
|
CPU.State <= UPP_C1;
|
|
|
|
when OP_LDA =>
|
when OP_LDA =>
|
IC := CACHE_OPER1;
|
CPU_Next_State <= LDA_C1;
|
PC := PC_IDLE;
|
Cache_Ctrl <= CACHE_OPER1;
|
CPU.State <= LDA_C1;
|
|
|
|
when OP_LDI =>
|
when OP_LDI =>
|
IC := CACHE_OPER1;
|
CPU_Next_State <= LDI_C1;
|
PC := PC_IDLE;
|
Cache_Ctrl <= CACHE_OPER1;
|
CPU.State <= LDI_C1;
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
when OP_LDO =>
|
when OP_LDO =>
|
IC := CACHE_OPER1;
|
CPU_Next_State <= LDO_C1;
|
PC := PC_IDLE;
|
Cache_Ctrl <= CACHE_OPER1;
|
CPU.State <= LDO_C1;
|
PC_Ctrl.Oper <= PC_REV2;
|
|
|
when OP_LDX =>
|
when OP_LDX =>
|
IC := CACHE_PFFLUSH;
|
CPU_Next_State <= LDX_C1;
|
PC := PC_REV1;
|
PC_Ctrl.Oper <= PC_REV2;
|
CPU.State <= LDX_C1;
|
-- If auto-increment is disabled, use the specified register pair,
|
|
-- otherwise, for an odd:even pair, and issue the first half of
|
|
-- a UPP instruction to the ALU
|
|
if( not Enable_Auto_Increment )then
|
|
Address <= Regfile(Reg_1) & Regfile(Reg);
|
|
else
|
|
Reg := conv_integer(SubOp(2 downto 1) & '0');
|
|
Reg_1 := conv_integer(SubOp(2 downto 1) & '1');
|
|
Address <= Regfile(Reg_1) & Regfile(Reg);
|
|
if( SubOp(0) = '1' )then
|
|
ALU_Ctrl.Oper<= ALU_UPP;
|
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
|
end if;
|
|
end if;
|
|
|
when OP_STA =>
|
when OP_STA =>
|
IC := CACHE_OPER1;
|
CPU_Next_State <= STA_C1;
|
PC := PC_IDLE;
|
Cache_Ctrl <= CACHE_OPER1;
|
CPU.State <= STA_C1;
|
|
|
|
when OP_STO =>
|
when OP_STO =>
|
IC := CACHE_OPER1;
|
CPU_Next_State <= STO_C1;
|
PC := PC_REV2;
|
Cache_Ctrl <= CACHE_OPER1;
|
DP.Src := DATA_WR_REG;
|
PC_Ctrl.Oper <= PC_REV2;
|
DP.Reg := ACCUM;
|
DP_Ctrl.Src <= DATA_WR_REG;
|
CPU.State <= STO_C1;
|
DP_Ctrl.Reg <= ACCUM;
|
|
|
when OP_STX =>
|
when OP_STX =>
|
IC := CACHE_PFFLUSH;
|
CPU_Next_State <= STX_C1;
|
PC := PC_REV2;
|
Cache_Ctrl <= CACHE_PREFETCH;
|
DP.Src := DATA_WR_REG;
|
PC_Ctrl.Oper <= PC_REV2;
|
DP.Reg := ACCUM;
|
DP_Ctrl.Src <= DATA_WR_REG;
|
CPU.State <= STX_C1;
|
DP_Ctrl.Reg <= ACCUM;
|
|
|
when others =>
|
when others =>
|
IC := CACHE_PREFETCH;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC := PC_REV1;
|
ALU_Ctrl.Oper <= Opcode;
|
CPU.State <= MATH_C1;
|
ALU_Ctrl.Reg <= SubOp;
|
|
|
end case;
|
end case;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Program Control (BR0_C1, BR1_C1, DBNZ_C1, JMP )
|
-- Program Control (BR0_C1, BR1_C1, DBNZ_C1, JMP )
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
when BRN_C1 =>
|
when BRN_C1 =>
|
if( Flags(RegSel) = CPU.Opcode(0) )then
|
CPU_Next_State <= INSTR_DECODE;
|
IC := CACHE_IDLE;
|
Cache_Ctrl <= CACHE_INSTR;
|
PC := PC_BRANCH;
|
PC_Ctrl.Oper <= PC_INCR;
|
CPU.State <= PIPE_FILL_0;
|
if( Flags(Reg) = Opcode(0) )then
|
else
|
CPU_Next_State <= PIPE_FILL_0;
|
IC := CACHE_INSTR;
|
Cache_Ctrl <= CACHE_IDLE;
|
CPU.State <= INSTR_DECODE;
|
PC_Ctrl.Offset <= Operand1;
|
end if;
|
end if;
|
|
|
when DBNZ_C1 =>
|
when DBNZ_C1 =>
|
IC := CACHE_PREFETCH;
|
CPU_Next_State <= INSTR_DECODE;
|
PC := PC_IDLE;
|
Cache_Ctrl <= CACHE_INSTR;
|
CPU.State <= DBNZ_C2;
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
when DBNZ_C2 =>
|
|
if( Flags(FL_ZERO) = '0' )then
|
if( Flags(FL_ZERO) = '0' )then
|
IC := CACHE_INVALIDATE;
|
CPU_Next_State <= PIPE_FILL_0;
|
PC := PC_BRANCH;
|
Cache_Ctrl <= CACHE_IDLE;
|
CPU.State <= PIPE_FILL_0;
|
PC_Ctrl.Offset <= Operand1;
|
else
|
|
PC := PC_REV1;
|
|
CPU.State <= PIPE_FILL_1;
|
|
end if;
|
end if;
|
|
|
when JMP_C1 =>
|
when JMP_C1 =>
|
IC := CACHE_OPER2;
|
CPU_Next_State <= JMP_C2;
|
PC := PC_IDLE;
|
Cache_Ctrl <= CACHE_OPER2;
|
CPU.State <= JMP_C2;
|
|
|
|
when JMP_C2 =>
|
when JMP_C2 =>
|
PC := PC_LOAD;
|
CPU_Next_State <= PIPE_FILL_0;
|
CPU.State <= PIPE_FILL_0;
|
PC_Ctrl.Oper <= PC_LOAD;
|
|
PC_Ctrl.Addr <= Operand2 & Operand1;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Data Storage - Load from memory (LDA, LDI, LDO, LDX)
|
-- Data Storage - Load from memory (LDA, LDI, LDO, LDX)
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
when LDA_C1 =>
|
when LDA_C1 =>
|
IC := CACHE_OPER2;
|
CPU_Next_State <= LDA_C2;
|
PC := PC_IDLE;
|
Cache_Ctrl <= CACHE_OPER2;
|
CPU.State <= LDA_C2;
|
|
|
|
when LDA_C2 =>
|
when LDA_C2 =>
|
PC := PC_IDLE;
|
CPU_Next_State <= LDA_C3;
|
CPU.State <= LDA_C3;
|
Address <= Operand2 & Operand1;
|
|
|
when LDA_C3 =>
|
when LDA_C3 =>
|
PC := PC_IDLE;
|
CPU_Next_State <= LDA_C4;
|
CPU.State <= LDA_C4;
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
when LDA_C4 =>
|
when LDA_C4 =>
|
IC := CACHE_OPER1;
|
CPU_Next_State <= LDI_C1;
|
PC := PC_INCR;
|
Cache_Ctrl <= CACHE_OPER1;
|
CPU.State <= LDI_C1;
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
when LDI_C1 =>
|
when LDI_C1 =>
|
IC := CACHE_PREFETCH;
|
CPU_Next_State <= INSTR_DECODE;
|
PC := PC_INCR;
|
Cache_Ctrl <= CACHE_INSTR;
|
CPU.A_Oper <= ALU_LDI;
|
PC_Ctrl.Oper <= PC_INCR;
|
CPU.A_Reg <= CPU.SubOp_p0;
|
ALU_Ctrl.Oper <= ALU_LDI;
|
CPU.A_Data <= CPU.Operand1;
|
ALU_Ctrl.Reg <= SubOp;
|
CPU.State <= PIPE_FILL_2;
|
ALU_Ctrl.Data <= Operand1;
|
|
|
when LDO_C1 =>
|
when LDO_C1 =>
|
IC := CACHE_PREFETCH;
|
CPU_Next_State <= LDX_C1;
|
PC := PC_REV2;
|
PC_Ctrl.Oper <= PC_INCR;
|
RegSel := conv_integer(CPU.SubOp_p0(2 downto 1) & '0');
|
if( Enable_Auto_Increment )then
|
if( Enable_Auto_Increment and CPU.AutoIncr = '1' )then
|
Reg := conv_integer(SubOp(2 downto 1) & '0');
|
CPU.A_Oper <= ALU_UPP1;
|
Reg_1 := conv_integer(SubOp(2 downto 1) & '1');
|
CPU.A_Reg <= CPU.SubOp_p0(2 downto 1) & '0';
|
Address <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
|
CPU.A_NoFlags <= '1';
|
if( SubOp(0) = '1' )then
|
CPU.A_Data <= CPU.RegFile(RegSel);
|
ALU_Ctrl.Oper<= ALU_UPP;
|
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
|
end if;
|
|
else
|
|
Address <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
|
end if;
|
end if;
|
CPU.State <= LDX_C2;
|
|
|
|
when LDX_C1 =>
|
when LDX_C1 =>
|
PC := PC_REV2;
|
CPU_Next_State <= LDX_C2;
|
RegSel := conv_integer(CPU.SubOp_p0(2 downto 1) & '0');
|
PC_Ctrl.Oper <= PC_INCR;
|
if( Enable_Auto_Increment and CPU.AutoIncr = '1' )then
|
|
CPU.A_Oper <= ALU_UPP1;
|
|
CPU.A_Reg <= CPU.SubOp_p0(2 downto 1) & '0';
|
|
CPU.A_NoFlags <= '1';
|
|
CPU.A_Data <= CPU.Regfile(RegSel);
|
|
end if;
|
|
CPU.State <= LDX_C2;
|
|
|
|
when LDX_C2 =>
|
when LDX_C2 =>
|
PC := PC_INCR;
|
CPU_Next_State <= LDX_C3;
|
RegSel := conv_integer(CPU.SubOp_p0(2 downto 1) & '1');
|
PC_Ctrl.Oper <= PC_INCR;
|
if( Enable_Auto_Increment and CPU.AutoIncr = '1' )then
|
Cache_Ctrl <= CACHE_OPER1;
|
CPU.A_Oper <= ALU_UPP2;
|
|
CPU.A_Reg <= CPU.SubOp_p0(2 downto 1) & '1';
|
|
CPU.A_Data <= CPU.Regfile(RegSel);
|
|
end if;
|
|
CPU.State <= LDX_C3;
|
|
|
|
when LDX_C3 =>
|
when LDX_C3 =>
|
IC := CACHE_OPER1;
|
CPU_Next_State <= INSTR_DECODE;
|
PC := PC_INCR;
|
Cache_Ctrl <= CACHE_INSTR;
|
CPU.State <= LDX_C4;
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= ALU_LDX;
|
when LDX_C4 =>
|
ALU_Ctrl.Reg <= ACCUM;
|
PC := PC_INCR;
|
ALU_Ctrl.Data <= Operand1;
|
CPU.A_Oper <= ALU_LDI;
|
|
CPU.A_Reg <= ACCUM;
|
|
CPU.A_Data <= CPU.Operand1;
|
|
CPU.State <= PIPE_FILL_2;
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Data Storage - Store to memory (STA, STO, STX)
|
-- Data Storage - Store to memory (STA, STO, STX)
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
when STA_C1 =>
|
when STA_C1 =>
|
IC := CACHE_OPER2;
|
CPU_Next_State <= STA_C2;
|
PC := PC_IDLE;
|
Cache_Ctrl <= CACHE_OPER2;
|
DP.Src := DATA_WR_REG;
|
DP_Ctrl.Src <= DATA_WR_REG;
|
DP.Reg := CPU.SubOp_p0;
|
DP_Ctrl.Reg <= SubOp;
|
CPU.State <= STA_C2;
|
|
|
|
when STA_C2 =>
|
when STA_C2 =>
|
IC := CACHE_PREFETCH;
|
CPU_Next_State <= STA_C3;
|
PC := PC_INCR;
|
Address <= Operand2 & Operand1;
|
CPU.State <= PIPE_FILL_1;
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
|
when STA_C3 =>
|
|
CPU_Next_State <= PIPE_FILL_2;
|
|
Cache_Ctrl <= CACHE_PREFETCH;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
when STO_C1 =>
|
when STO_C1 =>
|
IC := CACHE_PREFETCH;
|
Cache_Ctrl <= CACHE_PREFETCH;
|
PC := PC_INCR;
|
PC_Ctrl.Oper <= PC_INCR;
|
RegSel := conv_integer(CPU.SubOp_p0(2 downto 1) & '0');
|
-- If auto-increment is disabled, just load the registers normally
|
if( not Enable_Auto_Increment )then
|
if( not Enable_Auto_Increment )then
|
CPU.State <= PIPE_FILL_1;
|
CPU_Next_State <= PIPE_FILL_1;
|
|
Address <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
|
|
-- Otherwise, enforce the even register rule, and check the LSB to see
|
|
-- if we should perform the auto-increment on the register pair
|
else
|
else
|
CPU.State <= PIPE_FILL_0;
|
CPU_Next_State <= PIPE_FILL_0;
|
if( CPU.AutoIncr = '1' )then
|
Reg := conv_integer(SubOp(2 downto 1) & '0');
|
CPU.A_Oper <= ALU_UPP1;
|
Reg_1 := conv_integer(SubOp(2 downto 1) & '1');
|
CPU.A_Reg <= CPU.SubOp_p0(2 downto 1) & '0';
|
Address <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
|
CPU.A_NoFlags <= '1';
|
if( SubOp(0) = '1' )then
|
CPU.A_Data <= CPU.Regfile(RegSel);
|
CPU_Next_State <= STO_C2;
|
CPU.State <= STO_C2;
|
ALU_Ctrl.Oper <= ALU_UPP;
|
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when STO_C2 =>
|
when STO_C2 =>
|
PC := PC_INCR;
|
CPU_Next_State <= PIPE_FILL_1;
|
RegSel := conv_integer(CPU.SubOp_p0(2 downto 1) & '1');
|
PC_Ctrl.Oper <= PC_INCR;
|
CPU.A_Oper <= ALU_UPP2;
|
ALU_Ctrl.Oper <= ALU_UPP2;
|
CPU.A_Reg <= CPU.SubOp_p0(2 downto 1) & '1';
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '1';
|
CPU.A_Data <= CPU.Regfile(RegSel);
|
|
CPU.State <= PIPE_FILL_1;
|
|
|
|
when STX_C1 =>
|
when STX_C1 =>
|
PC := PC_INCR;
|
PC_Ctrl.Oper <= PC_INCR;
|
|
-- If auto-increment is disabled, just load the registers normally
|
if( not Enable_Auto_Increment )then
|
if( not Enable_Auto_Increment )then
|
CPU.State <= PIPE_FILL_1;
|
CPU_Next_State <= PIPE_FILL_1;
|
|
Address <= (Regfile(Reg_1) & Regfile(Reg));
|
|
-- Otherwise, enforce the even register rule, and check the LSB to see
|
|
-- if we should perform the auto-increment on the register pair
|
else
|
else
|
RegSel := conv_integer(CPU.SubOp_p0(2 downto 1) & '0');
|
CPU_Next_State <= PIPE_FILL_1;
|
CPU.State <= PIPE_FILL_1;
|
Reg := conv_integer(SubOp(2 downto 1) & '0');
|
if( CPU.AutoIncr = '1' )then
|
Reg_1 := conv_integer(SubOp(2 downto 1) & '1');
|
CPU.A_Oper <= ALU_UPP1;
|
Address <= (Regfile(Reg_1) & Regfile(Reg));
|
CPU.A_Reg <= CPU.SubOp_p0(2 downto 1) & '0';
|
if( SubOp(0) = '1' )then
|
CPU.A_NoFlags <= '1';
|
CPU_Next_State <= STX_C2;
|
CPU.A_Data <= CPU.Regfile(RegSel);
|
ALU_Ctrl.Oper <= ALU_UPP;
|
CPU.State <= STX_C2;
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when STX_C2 =>
|
when STX_C2 =>
|
PC := PC_INCR;
|
CPU_Next_State <= PIPE_FILL_2;
|
RegSel := conv_integer(CPU.SubOp_p0(2 downto 1) & '1');
|
PC_Ctrl.Oper <= PC_INCR;
|
CPU.A_Oper <= ALU_UPP2;
|
ALU_Ctrl.Oper <= ALU_UPP2;
|
CPU.A_Reg <= CPU.SubOp_p0(2 downto 1) & '1';
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '1';
|
CPU.A_Data <= CPU.Regfile(RegSel);
|
|
CPU.State <= PIPE_FILL_2;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Multi-Cycle Math Operations
|
|
-------------------------------------------------------------------------------
|
|
|
|
when MATH_C1 =>
|
|
PC := PC_INCR;
|
|
CPU.A_Oper <= CPU.Opcode;
|
|
CPU.A_Reg <= CPU.SubOp_p0;
|
|
CPU.A_Data <= CPU.Regfile(RegSel);
|
|
CPU.State <= PIPE_FILL_2;
|
|
|
|
when GMSK_C1 =>
|
|
PC := PC_INCR;
|
|
CPU.A_Oper <= ALU_LDI;
|
|
CPU.A_Data <= CPU.Int_Mask;
|
|
CPU.State <= PIPE_FILL_2;
|
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Multi-Cycle Math Operations (UPP, MUL)
|
|
-------------------------------------------------------------------------------
|
|
|
|
-- Because we have to backup the pipeline by 1 to refetch the 2nd
|
|
-- instruction/first operand, we have to return through PF2
|
when MUL_C1 =>
|
when MUL_C1 =>
|
PC := PC_INCR;
|
CPU_Next_State <= PIPE_FILL_2;
|
CPU.A_Oper <= ALU_MUL;
|
PC_Ctrl.Oper <= PC_INCR;
|
CPU.State <= PIPE_FILL_2;
|
ALU_Ctrl.Oper <= ALU_MUL;
|
|
|
when UPP_C1 =>
|
when UPP_C1 =>
|
PC := PC_INCR;
|
CPU_Next_State <= PIPE_FILL_2;
|
RegSel := conv_integer(CPU.SubOp_p1);
|
PC_Ctrl.Oper <= PC_INCR;
|
CPU.A_Oper <= ALU_UPP2;
|
ALU_Ctrl.Oper <= ALU_UPP2;
|
CPU.A_Reg <= CPU.SubOp_p1;
|
ALU_Ctrl.Reg <= SubOp_p1;
|
CPU.A_Data <= CPU.Regfile(RegSel);
|
|
CPU.State <= PIPE_FILL_2;
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Basic Stack Manipulation (PSH, POP, RSP)
|
-- Basic Stack Manipulation (PSH, POP, RSP)
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
when PSH_C1 =>
|
when PSH_C1 =>
|
PC := PC_REV1;
|
CPU_Next_State <= PIPE_FILL_1;
|
SP := SP_PUSH;
|
Address <= Stack_Ptr;
|
CPU.State <= PIPE_FILL_1;
|
SP_Ctrl.Oper <= SP_PUSH;
|
|
|
when POP_C1 =>
|
when POP_C1 =>
|
PC := PC_IDLE;
|
CPU_Next_State <= POP_C2;
|
CPU.State <= POP_C2;
|
Address <= Stack_Ptr;
|
|
|
when POP_C2 =>
|
when POP_C2 =>
|
PC := PC_IDLE;
|
CPU_Next_State <= POP_C3;
|
CPU.State <= POP_C3;
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
when POP_C3 =>
|
when POP_C3 =>
|
IC := CACHE_OPER1;
|
CPU_Next_State <= POP_C4;
|
PC := PC_INCR;
|
Cache_Ctrl <= CACHE_OPER1;
|
CPU.State <= POP_C4;
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
when POP_C4 =>
|
when POP_C4 =>
|
PC := PC_INCR;
|
CPU_Next_State <= INSTR_DECODE;
|
CPU.A_Oper <= ALU_LDI;
|
Cache_Ctrl <= CACHE_INSTR;
|
CPU.A_Reg <= CPU.SubOp_p0;
|
PC_Ctrl.Oper <= PC_INCR;
|
CPU.A_NoFlags <= '1';
|
ALU_Ctrl.Oper <= ALU_POP;
|
CPU.A_Data <= CPU.Operand1;
|
ALU_Ctrl.Reg <= SubOp;
|
CPU.State <= PIPE_FILL_2;
|
ALU_Ctrl.Data <= Operand1;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Subroutines & Interrupts (RTS, JSR)
|
-- Subroutines & Interrupts (RTS, JSR)
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
when WAIT_FOR_INT =>
|
when WAIT_FOR_INT => -- For soft interrupts only, halt the Program_Ctr
|
PC := PC_IDLE;
|
DP_Ctrl.Src <= DATA_BUS_IDLE;
|
DP.Src := DATA_BUS_IDLE;
|
CPU_Next_State <= WAIT_FOR_INT;
|
CPU.State <= WAIT_FOR_INT;
|
|
|
|
when ISR_C1 =>
|
when ISR_C1 =>
|
PC := PC_IDLE;
|
CPU_Next_State <= ISR_C2;
|
INT.Incr_ISR := '1';
|
Address <= ISR_Addr;
|
CPU.State <= ISR_C2;
|
INT_Ctrl.Incr_ISR <= '1';
|
|
|
when ISR_C2 =>
|
when ISR_C2 =>
|
PC := PC_IDLE;
|
CPU_Next_State <= ISR_C3;
|
DP.Src := DATA_WR_FLAG;
|
Address <= ISR_Addr;
|
CPU.State <= ISR_C3;
|
DP_Ctrl.Src <= DATA_WR_FLAG;
|
|
|
when ISR_C3 =>
|
when ISR_C3 =>
|
IC := CACHE_OPER1;
|
CPU_Next_State <= JSR_C1;
|
PC := PC_IDLE;
|
Cache_Ctrl <= CACHE_OPER1;
|
SP := SP_PUSH;
|
Address <= Stack_Ptr;
|
DP.Src := DATA_WR_PC_UPPER;
|
SP_Ctrl.Oper <= SP_PUSH;
|
Ack_D := '1';
|
DP_Ctrl.Src <= DATA_WR_PC;
|
CPU.A_Oper <= ALU_STP;
|
DP_Ctrl.Reg <= ACCUM+1;
|
CPU.A_Reg <= INT_FLAG;
|
ALU_Ctrl.Oper <= ALU_STP;
|
CPU.State <= JSR_C1;
|
ALU_Ctrl.Reg <= INT_FLAG;
|
|
Ack_D <= '1';
|
|
|
when JSR_C1 =>
|
when JSR_C1 =>
|
IC := CACHE_OPER2;
|
CPU_Next_State <= JSR_C2;
|
PC := PC_IDLE;
|
Cache_Ctrl <= CACHE_OPER2;
|
SP := SP_PUSH;
|
Address <= Stack_Ptr;
|
DP.Src := DATA_WR_PC_LOWER;
|
SP_Ctrl.Oper <= SP_PUSH;
|
CPU.State <= JSR_C2;
|
DP_Ctrl.Src <= DATA_WR_PC;
|
|
DP_Ctrl.Reg <= ACCUM;
|
|
|
when JSR_C2 =>
|
when JSR_C2 =>
|
SP := SP_PUSH;
|
CPU_Next_State <= PIPE_FILL_0;
|
PC := PC_LOAD;
|
Address <= Stack_Ptr;
|
CPU.State <= PIPE_FILL_0;
|
SP_Ctrl.Oper <= SP_PUSH;
|
|
PC_Ctrl.Oper <= PC_LOAD;
|
|
PC_Ctrl.Addr <= Operand2 & Operand1;
|
|
|
when RTS_C1 =>
|
when RTS_C1 =>
|
PC := PC_IDLE;
|
CPU_Next_State <= RTS_C2;
|
SP := SP_POP;
|
Address <= Stack_Ptr;
|
CPU.State <= RTS_C2;
|
SP_Ctrl.Oper <= SP_POP;
|
|
|
when RTS_C2 =>
|
when RTS_C2 =>
|
PC := PC_IDLE;
|
CPU_Next_State <= RTS_C3;
|
if( CPU.SubOp_p0 = SOP_RTI )then
|
Address <= Stack_Ptr;
|
SP := SP_POP;
|
-- if this is an RTI, then we need to POP the flags
|
|
if( SubOp = SOP_RTI )then
|
|
SP_Ctrl.Oper <= SP_POP;
|
end if;
|
end if;
|
CPU.State <= RTS_C3;
|
|
|
|
when RTS_C3 =>
|
when RTS_C3 =>
|
IC := CACHE_OPER1;
|
CPU_Next_State <= RTS_C4;
|
PC := PC_IDLE;
|
Cache_Ctrl <= CACHE_OPER1;
|
CPU.State <= RTS_C4;
|
-- It doesn't really matter what is on the address bus for RTS, while
|
|
-- it does for RTI, so we make this the default
|
|
Address <= Stack_Ptr;
|
|
|
when RTS_C4 =>
|
when RTS_C4 =>
|
IC := CACHE_OPER2;
|
CPU_Next_State <= RTS_C5;
|
PC := PC_IDLE;
|
Cache_Ctrl <= CACHE_OPER2;
|
CPU.State <= RTS_C5;
|
|
|
|
when RTS_C5 =>
|
when RTS_C5 =>
|
PC := PC_LOAD;
|
CPU_Next_State <= PIPE_FILL_0;
|
CPU.State <= PIPE_FILL_0;
|
PC_Ctrl.Oper <= PC_LOAD;
|
if( CPU.SubOp_p0 = SOP_RTI )then
|
PC_Ctrl.Addr <= Operand2 & Operand1;
|
IC := CACHE_OPER1;
|
if( SubOp = SOP_RTI )then
|
CPU.State <= RTI_C6;
|
CPU_Next_State <= RTI_C6;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
end if;
|
end if;
|
|
|
when RTI_C6 =>
|
when RTI_C6 =>
|
PC := PC_INCR;
|
CPU_Next_State <= PIPE_FILL_1;
|
CPU.Int_Level <= 7;
|
PC_Ctrl.Oper <= PC_INCR;
|
CPU.A_Oper <= ALU_RFLG;
|
ALU_Ctrl.Oper <= ALU_RFLG;
|
CPU.A_Data <= CPU.Operand1;
|
ALU_Ctrl.Data <= Operand1;
|
CPU.State <= PIPE_FILL_1;
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Debugging (BRK) Performs a 5-clock NOP
|
-- Debugging (BRK) Performs a 5-clock NOP
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
when BRK_C1 =>
|
when BRK_C1 =>
|
PC := PC_IDLE;
|
CPU_Next_State <= PIPE_FILL_0;
|
CPU.State <= PIPE_FILL_0;
|
|
|
|
when others =>
|
when others =>
|
null;
|
null;
|
|
|
end case;
|
end case;
|
|
|
-------------------------------------------------------------------------------
|
-- Interrupt service routines can only begin during the decode and wait
|
-- Interrupt Override Logic
|
-- states to avoid corruption due to incomplete instruction execution
|
-------------------------------------------------------------------------------
|
|
|
|
if( Int_Req = '1' )then
|
if( Int_Req = '1' )then
|
if( CPU.State = INSTR_DECODE or CPU.State = WAIT_FOR_INT )then
|
if( CPU_State = INSTR_DECODE or CPU_State = WAIT_FOR_INT )then
|
IC := CACHE_IDLE;
|
-- Reset all of the sub-block controls to IDLE, to avoid unintended
|
PC := PC_REV3;
|
-- operation due to the current instruction
|
SP := SP_IDLE;
|
ALU_Ctrl.Oper <= ALU_IDLE;
|
DP.Src := DATA_RD_MEM;
|
Cache_Ctrl <= CACHE_IDLE;
|
INT.Soft_Ints := (others => '0');
|
SP_Ctrl.Oper <= SP_IDLE;
|
CPU.A_Oper <= ALU_IDLE;
|
DP_Ctrl.Src <= DATA_RD_MEM;
|
CPU.State <= ISR_C1;
|
INT_Ctrl.Soft_Ints <= (others => '0');
|
|
-- Rewind the PC by 3 to compensate for the pipeline registers
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
PC_Ctrl.Offset <= x"FF";
|
|
CPU_Next_State <= ISR_C1;
|
|
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-------------------------------------------------------------------------------
|
end process;
|
-- Vectored Interrupt Controller
|
|
-------------------------------------------------------------------------------
|
|
|
|
CPU.Int_Pending <= ((Interrupts or INT.Soft_Ints) and
|
|
CPU.Int_Mask) or CPU.Int_Pending;
|
|
|
|
if( CPU.Wait_for_FSM = '0' )then
|
|
if( CPU.Int_Pending(0) = '1' )then
|
|
CPU.Int_Addr <= INT_VECTOR_0;
|
|
CPU.Int_Level <= 0;
|
|
CPU.Int_Pending(0) <= '0';
|
|
CPU.Wait_for_FSM <= '1';
|
|
elsif( CPU.Int_Pending(1) = '1' and CPU.Int_Level > 0 )then
|
|
CPU.Int_Addr <= INT_VECTOR_1;
|
|
CPU.Int_Level <= 1;
|
|
CPU.Int_Pending(1) <= '0';
|
|
CPU.Wait_for_FSM <= '1';
|
|
elsif( CPU.Int_Pending(2) = '1' and CPU.Int_Level > 1 )then
|
|
CPU.Int_Addr <= INT_VECTOR_2;
|
|
CPU.Int_Level <= 2;
|
|
CPU.Int_Pending(2) <= '0';
|
|
CPU.Wait_for_FSM <= '1';
|
|
elsif( CPU.Int_Pending(3) = '1' and CPU.Int_Level > 2 )then
|
|
CPU.Int_Addr <= INT_VECTOR_3;
|
|
CPU.Int_Level <= 3;
|
|
CPU.Int_Pending(3) <= '0';
|
|
CPU.Wait_for_FSM <= '1';
|
|
elsif( CPU.Int_Pending(4) = '1' and CPU.Int_Level > 3 )then
|
|
CPU.Int_Addr <= INT_VECTOR_4;
|
|
CPU.Int_Level <= 4;
|
|
CPU.Int_Pending(4) <= '0';
|
|
CPU.Wait_for_FSM <= '1';
|
|
elsif( CPU.Int_Pending(5) = '1' and CPU.Int_Level > 4 )then
|
|
CPU.Int_Addr <= INT_VECTOR_5;
|
|
CPU.Int_Level <= 5;
|
|
CPU.Int_Pending(5) <= '0';
|
|
CPU.Wait_for_FSM <= '1';
|
|
elsif( CPU.Int_Pending(6) = '1' and CPU.Int_Level > 6 )then
|
|
CPU.Int_Addr <= INT_VECTOR_6;
|
|
CPU.Int_Level <= 6;
|
|
CPU.Int_Pending(6) <= '0';
|
|
CPU.Wait_for_FSM <= '1';
|
|
elsif( CPU.Int_Pending(7) = '1' )then
|
|
CPU.Int_Addr <= INT_VECTOR_7;
|
|
CPU.Int_Level <= 7;
|
|
CPU.Int_Pending(7) <= '0';
|
|
CPU.Wait_for_FSM <= '1';
|
|
end if;
|
|
end if;
|
|
|
|
Ack_Q <= Ack_D;
|
|
Ack_Q1 <= Ack_Q;
|
|
Int_Ack <= Ack_Q1;
|
|
if( Int_Ack = '1' )then
|
|
CPU.Wait_for_FSM <= '0';
|
|
end if;
|
|
|
|
Int_Req <= CPU.Wait_for_FSM and (not Int_Ack);
|
|
|
|
if( INT.Mask_Set = '1' )then
|
|
if( Enable_NMI )then
|
|
CPU.Int_Mask <= Accumulator(7 downto 1) & '1';
|
|
else -- Disable NMI override
|
|
CPU.Int_Mask <= Accumulator;
|
|
end if;
|
|
end if;
|
|
|
|
if( INT.Incr_ISR = '1' )then
|
-- We need to infer a hardware multipler, so we create a special clocked
|
CPU.Int_Addr <= CPU.Int_Addr + 1;
|
-- process with no reset or clock enable
|
|
Multiplier_proc: process( Clock )
|
|
begin
|
|
if( rising_edge(Clock) )then
|
|
Mult <= Regfile(0) *
|
|
Regfile(conv_integer(ALU_Ctrl.Reg));
|
end if;
|
end if;
|
|
end process;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- ALU (Arithmetic / Logic Unit)
|
-- Registered portion of CPU finite state machine
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
Index := conv_integer(CPU.A_Reg);
|
CPU_Regs: process( Reset, Clock )
|
|
variable Offset_SX : ADDRESS_TYPE;
|
CPU.M_Prod <= Accumulator *
|
variable i_Ints : INTERRUPT_BUNDLE := (others => '0');
|
CPU.Regfile(conv_integer(CPU.M_Reg));
|
variable Index : integer range 0 to 7 := 0;
|
|
variable Sum : std_logic_vector(8 downto 0) := "000000000";
|
case( CPU.A_Oper )is
|
variable Temp : std_logic_vector(8 downto 0) := "000000000";
|
when ALU_INC => -- Rn = Rn + 1 : CPU.Flags N,C,Z
|
begin
|
Temp := ("0" & x"01") +
|
if( Reset = Reset_Level )then
|
("0" & CPU.A_Data);
|
CPU_State <= PIPE_FILL_0;
|
Flags(FL_CARRY) <= Temp(8);
|
Opcode <= OP_INC;
|
CPU.Regfile(Index) <= Temp(7 downto 0);
|
SubOp <= ACCUM;
|
if( CPU.A_NoFlags = '0' )then
|
SubOp_p1 <= ACCUM;
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
Operand1 <= x"00";
|
Flags(FL_NEG) <= Temp(7);
|
Operand2 <= x"00";
|
end if;
|
Instr_Prefetch <= '0';
|
|
Prefetch <= x"00";
|
when ALU_UPP2 => -- Rn = Rn + C : Flags C
|
|
Temp := ("0" & x"00") +
|
|
("0" & CPU.A_Data) +
|
|
Flags(FL_CARRY);
|
|
Flags(FL_CARRY) <= Temp(8);
|
|
CPU.Regfile(Index) <= Temp(7 downto 0);
|
|
|
|
when ALU_ADC => -- R0 = R0 + Rn + C : N,C,Z
|
|
Temp := ("0" & Accumulator) +
|
|
("0" & CPU.A_Data) +
|
|
Flags(FL_CARRY);
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_CARRY) <= Temp(8);
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Accumulator <= Temp(7 downto 0);
|
|
|
|
when ALU_TX0 => -- R0 = Rn : Flags N,Z
|
|
Temp := "0" & CPU.A_Data;
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Accumulator <= Temp(7 downto 0);
|
|
|
|
when ALU_OR => -- R0 = R0 | Rn : Flags N,Z
|
|
Temp(7 downto 0) := Accumulator or CPU.A_Data;
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Accumulator <= Temp(7 downto 0);
|
|
|
|
when ALU_AND => -- R0 = R0 & Rn : Flags N,Z
|
|
Temp(7 downto 0) := Accumulator and CPU.A_Data;
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Accumulator <= Temp(7 downto 0);
|
|
|
|
when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z
|
|
Temp(7 downto 0) := Accumulator xor CPU.A_Data;
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Accumulator <= Temp(7 downto 0);
|
|
|
|
when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z
|
|
Temp := CPU.A_Data & Flags(FL_CARRY);
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_CARRY) <= Temp(8);
|
|
Flags(FL_NEG) <= Temp(7);
|
|
CPU.Regfile(Index) <= Temp(7 downto 0);
|
|
|
|
when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z
|
|
Temp := CPU.A_Data(0) & Flags(FL_CARRY) &
|
|
CPU.A_Data(7 downto 1);
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_CARRY) <= Temp(8);
|
|
Flags(FL_NEG) <= Temp(7);
|
|
CPU.Regfile(Index) <= Temp(7 downto 0);
|
|
|
|
when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
|
|
Temp := ("0" & CPU.A_Data) +
|
|
("0" & x"FF");
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_CARRY) <= Temp(8);
|
|
Flags(FL_NEG) <= Temp(7);
|
|
CPU.Regfile(Index) <= Temp(7 downto 0);
|
|
|
|
when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
|
|
Temp := ("0" & Accumulator) +
|
|
("0" & (not CPU.A_Data)) +
|
|
Flags(FL_CARRY);
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_CARRY) <= Temp(8);
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Accumulator <= Temp(7 downto 0);
|
|
|
|
when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z
|
|
Temp := ("0" & Accumulator) +
|
|
("0" & CPU.A_Data);
|
|
Flags(FL_CARRY) <= Temp(8);
|
|
Accumulator <= Temp(7 downto 0);
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_NEG) <= Temp(7);
|
|
|
|
when ALU_STP => -- Sets bit(n) in the CPU.Flags register
|
|
Flags(Index) <= '1';
|
|
|
|
when ALU_BTT => -- Z = !R0(N), N = R0(7)
|
|
Flags(FL_ZERO) <= not Accumulator(Index);
|
|
Flags(FL_NEG) <= Accumulator(7);
|
|
|
|
when ALU_CLP => -- Clears bit(n) in the Flags register
|
|
Flags(Index) <= '0';
|
|
|
|
when ALU_T0X => -- Rn = R0 : Flags N,Z
|
Wr_Data <= (others => '0');
|
Temp := "0" & Accumulator;
|
Wr_Enable <= '0';
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
Rd_Enable <= '1';
|
Flags(FL_NEG) <= Temp(7);
|
|
CPU.Regfile(Index) <= Temp(7 downto 0);
|
|
|
|
when ALU_CMP => -- Sets CPU.Flags on R0 - Rn : Flags N,C,Z
|
Program_Ctr <= Program_Start_Addr;
|
Temp := ("0" & Accumulator) +
|
Stack_Ptr <= Stack_Start_Addr;
|
("0" & (not CPU.A_Data)) +
|
|
'1';
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_CARRY) <= Temp(8);
|
|
Flags(FL_NEG) <= Temp(7);
|
|
|
|
when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
|
Ack_Q <= '0';
|
CPU.Regfile(0) <= CPU.M_Prod(7 downto 0);
|
Ack_Q1 <= '0';
|
CPU.Regfile(1) <= CPU.M_Prod(15 downto 8);
|
Int_Ack <= '0';
|
Flags(FL_ZERO) <= nor_reduce(CPU.M_Prod);
|
|
|
|
when ALU_LDI => -- Rn <= Data : Flags N,Z
|
Int_Req <= '0';
|
if( CPU.A_NoFlags = '0' )then
|
Pending <= x"00";
|
Flags(FL_ZERO) <= nor_reduce(CPU.A_Data);
|
Wait_for_FSM <= '0';
|
Flags(FL_NEG) <= CPU.A_Data(7);
|
if( Enable_NMI )then
|
|
Int_Mask <= Default_Interrupt_Mask(7 downto 1) & '1';
|
|
else
|
|
Int_Mask <= Default_Interrupt_Mask;
|
end if;
|
end if;
|
CPU.Regfile(Index) <= CPU.A_Data;
|
ISR_Addr <= INT_VECTOR_0;
|
|
|
when ALU_RFLG =>
|
for i in 0 to 7 loop
|
Flags <= CPU.A_Data;
|
Regfile(i) <= (others => '0');
|
|
end loop;
|
|
Flags <= x"00";
|
|
|
when others =>
|
elsif( rising_edge(Clock) )then
|
null;
|
Wr_Enable <= '0';
|
end case;
|
Wr_Data <= x"00";
|
|
Rd_Enable <= '0';
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Instruction/Operand caching for pipelined memory access
|
-- Instruction/Operand caching for pipelined memory access
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
CPU_State <= CPU_Next_State;
|
case( IC )is
|
case Cache_Ctrl is
|
when CACHE_INSTR =>
|
when CACHE_INSTR =>
|
CPU.Opcode <= Rd_Data(7 downto 3);
|
Opcode <= Rd_Data(7 downto 3);
|
CPU.SubOp_p0 <= Rd_Data(2 downto 0);
|
SubOp <= Rd_Data(2 downto 0);
|
CPU.SubOp_p1 <= Rd_Data(2 downto 0) + 1;
|
SubOp_p1 <= Rd_Data(2 downto 0) + 1;
|
if( CPU.Cache_Valid = '1' )then
|
if( Instr_Prefetch = '1' )then
|
CPU.Opcode <= CPU.Prefetch(7 downto 3);
|
Opcode <= Prefetch(7 downto 3);
|
CPU.SubOp_p0 <= CPU.Prefetch(2 downto 0);
|
SubOp <= Prefetch(2 downto 0);
|
CPU.SubOp_p1 <= CPU.Prefetch(2 downto 0) + 1;
|
SubOp_p1 <= Prefetch(2 downto 0) + 1;
|
CPU.Cache_Valid <= '0';
|
Instr_Prefetch <= '0';
|
end if;
|
end if;
|
|
|
when CACHE_OPER1 =>
|
when CACHE_OPER1 =>
|
CPU.Operand1 <= Rd_Data;
|
Operand1 <= Rd_Data;
|
|
|
when CACHE_OPER2 =>
|
when CACHE_OPER2 =>
|
CPU.Operand2 <= Rd_Data;
|
Operand2 <= Rd_Data;
|
|
|
when CACHE_PREFETCH =>
|
when CACHE_PREFETCH =>
|
CPU.Prefetch <= Rd_Data;
|
Prefetch <= Rd_Data;
|
CPU.Cache_Valid <= '1';
|
Instr_Prefetch <= '1';
|
|
|
when CACHE_PFFLUSH =>
|
|
CPU.Prefetch <= Rd_Data;
|
|
CPU.Operand1 <= x"00";
|
|
CPU.Operand2 <= x"00";
|
|
CPU.Cache_Valid <= '1';
|
|
|
|
when CACHE_INVALIDATE =>
|
|
CPU.Cache_Valid <= '0';
|
|
|
|
when CACHE_IDLE =>
|
when CACHE_IDLE =>
|
null;
|
null;
|
end case;
|
end case;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Program Counter
|
-- Program Counter
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
Offset_SX(15 downto 8) := (others => PC_Ctrl.Offset(7));
|
|
Offset_SX(7 downto 0) := PC_Ctrl.Offset;
|
|
|
Offset_SX(15 downto 8) := (others => CPU.Operand1(7));
|
case PC_Ctrl.Oper is
|
Offset_SX(7 downto 0) := CPU.Operand1;
|
|
|
|
case( PC )is
|
|
|
|
when PC_INCR =>
|
|
CPU.Program_Ctr <= CPU.Program_ctr + 1;
|
|
|
|
when PC_IDLE =>
|
when PC_IDLE =>
|
--CPU.Program_Ctr <= CPU.Program_Ctr + 0;
|
|
null;
|
null;
|
|
|
when PC_REV1 =>
|
when PC_REV1 =>
|
CPU.Program_Ctr <= CPU.Program_Ctr - 1;
|
Program_Ctr <= Program_Ctr - 1;
|
|
|
when PC_REV2 =>
|
when PC_REV2 =>
|
CPU.Program_Ctr <= CPU.Program_Ctr - 2;
|
Program_Ctr <= Program_Ctr - 2;
|
|
|
when PC_REV3 =>
|
when PC_INCR =>
|
CPU.Program_Ctr <= CPU.Program_Ctr - 3;
|
Program_Ctr <= Program_Ctr + Offset_SX - 2;
|
|
|
when PC_BRANCH =>
|
|
CPU.Program_Ctr <= CPU.Program_Ctr + Offset_SX - 2;
|
|
|
|
when PC_LOAD =>
|
when PC_LOAD =>
|
CPU.Program_Ctr <= CPU.Operand2 & CPU.Operand1;
|
Program_Ctr <= PC_Ctrl.Addr;
|
|
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- (Write) Data Path
|
-- (Write) Data Path
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
case DP_Ctrl.Src is
|
Wr_Data <= x"00";
|
|
Wr_Enable <= '0';
|
|
Rd_Enable <= '0';
|
|
|
|
case( DP.Src )is
|
|
when DATA_BUS_IDLE =>
|
when DATA_BUS_IDLE =>
|
null;
|
null;
|
|
|
when DATA_RD_MEM =>
|
when DATA_RD_MEM =>
|
Rd_Enable <= '1';
|
Rd_Enable <= '1';
|
|
|
when DATA_WR_REG =>
|
when DATA_WR_REG =>
|
Wr_Enable <= '1';
|
Wr_Enable <= '1';
|
Wr_Data <= CPU.Regfile(conv_integer(DP.Reg));
|
Wr_Data <= Regfile(conv_integer(DP_Ctrl.Reg));
|
|
|
when DATA_WR_FLAG =>
|
when DATA_WR_FLAG =>
|
Wr_Enable <= '1';
|
Wr_Enable <= '1';
|
Wr_Data <= Flags;
|
Wr_Data <= Flags;
|
|
|
when DATA_WR_PC_LOWER =>
|
when DATA_WR_PC =>
|
Wr_Enable <= '1';
|
|
Wr_Data <= CPU.Program_Ctr(7 downto 0);
|
|
|
|
when DATA_WR_PC_UPPER =>
|
|
Wr_Enable <= '1';
|
Wr_Enable <= '1';
|
Wr_Data <= CPU.Program_Ctr(15 downto 8);
|
Wr_Data <= Program_Ctr(15 downto 8);
|
|
if( DP_Ctrl.Reg = ACCUM )then
|
|
Wr_Data <= Program_Ctr(7 downto 0);
|
|
end if;
|
|
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Stack Pointer
|
-- Stack Pointer
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
case( SP )is
|
case SP_Ctrl.Oper is
|
when SP_IDLE =>
|
when SP_IDLE =>
|
null;
|
null;
|
|
|
when SP_RSET =>
|
when SP_RSET =>
|
CPU.Stack_Ptr <= Stack_Start_Addr;
|
-- The original RSP instruction simply reset the stack pointer to the preset
|
|
-- address set at compile time. However, with little extra effort, we can
|
|
-- modify the instruction to allow the stack pointer to be moved anywhere in
|
|
-- the memory map. Since RSP can't have an sub-opcode, R1:R0 was chosen as
|
|
-- a fixed source
|
|
Stack_Ptr <= Stack_Start_Addr;
|
if( Allow_Stack_Address_Move )then
|
if( Allow_Stack_Address_Move )then
|
CPU.Stack_Ptr <= CPU.Regfile(1) & CPU.Regfile(0);
|
Stack_Ptr <= Regfile(1) & Regfile(0);
|
end if;
|
end if;
|
|
|
when SP_POP =>
|
when SP_POP =>
|
CPU.Stack_Ptr <= CPU.Stack_Ptr + 1;
|
Stack_Ptr <= Stack_Ptr + 1;
|
|
|
when SP_PUSH =>
|
when SP_PUSH =>
|
CPU.Stack_Ptr <= CPU.Stack_Ptr - 1;
|
Stack_Ptr <= Stack_Ptr - 1;
|
|
|
when others =>
|
when others =>
|
null;
|
null;
|
|
|
end case;
|
end case;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Interrupt Controller
|
|
-------------------------------------------------------------------------------
|
|
-- The interrupt control mask is always sourced out of R0
|
|
if( INT_Ctrl.Mask_Set = '1' )then
|
|
-- If the Enable_NMI generic is set, force the LSB high
|
|
if( Enable_NMI )then
|
|
Int_Mask <= Regfile(conv_integer(ACCUM))(7 downto 1) & '1';
|
|
else
|
|
Int_Mask <= Regfile(conv_integer(ACCUM));
|
|
end if;
|
|
end if;
|
|
|
|
-- Combine external and internal interrupts, and mask the OR of the two
|
|
-- with the mask. Record any incoming interrupts to the pending buffer
|
|
i_Ints := (Interrupts or INT_Ctrl.Soft_Ints) and
|
|
Int_Mask;
|
|
|
|
Pending <= i_Ints or Pending;
|
|
|
|
if( Wait_for_FSM = '0' )then
|
|
if( Pending(0) = '1' )then
|
|
ISR_Addr <= INT_VECTOR_0;
|
|
Pending(0) <= '0';
|
|
Wait_for_FSM <= '1';
|
|
elsif( Pending(1) = '1' )then
|
|
ISR_Addr <= INT_VECTOR_1;
|
|
Pending(1) <= '0';
|
|
Wait_for_FSM <= '1';
|
|
elsif( Pending(2) = '1' )then
|
|
ISR_Addr <= INT_VECTOR_2;
|
|
Pending(2) <= '0';
|
|
Wait_for_FSM <= '1';
|
|
elsif( Pending(3) = '1' )then
|
|
ISR_Addr <= INT_VECTOR_3;
|
|
Pending(3) <= '0';
|
|
Wait_for_FSM <= '1';
|
|
elsif( Pending(4) = '1' )then
|
|
ISR_Addr <= INT_VECTOR_4;
|
|
Pending(4) <= '0';
|
|
Wait_for_FSM <= '1';
|
|
elsif( Pending(5) = '1' )then
|
|
ISR_Addr <= INT_VECTOR_5;
|
|
Pending(5) <= '0';
|
|
Wait_for_FSM <= '1';
|
|
elsif( Pending(6) = '1' )then
|
|
ISR_Addr <= INT_VECTOR_6;
|
|
Pending(6) <= '0';
|
|
Wait_for_FSM <= '1';
|
|
elsif( Pending(7) = '1' )then
|
|
ISR_Addr <= INT_VECTOR_7;
|
|
Pending(7) <= '0';
|
|
Wait_for_FSM <= '1';
|
|
end if;
|
|
end if;
|
|
|
|
-- Reset the Wait_for_FSM flag on Int_Ack
|
|
Ack_Q <= Ack_D;
|
|
Ack_Q1 <= Ack_Q;
|
|
Int_Ack <= Ack_Q1;
|
|
if( Int_Ack = '1' )then
|
|
Wait_for_FSM <= '0';
|
|
end if;
|
|
|
|
Int_Req <= Wait_for_FSM and (not Int_Ack);
|
|
|
|
-- Incr_ISR allows the CPU Core to advance the vector address to pop the
|
|
-- lower half of the address.
|
|
if( INT_Ctrl.Incr_ISR = '1' )then
|
|
ISR_Addr <= ISR_Addr + 1;
|
|
end if;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- ALU (Arithmetic / Logic Unit)
|
|
-------------------------------------------------------------------------------
|
|
Index := conv_integer(ALU_Ctrl.Reg);
|
|
Sum := (others => '0');
|
|
Temp := (others => '0');
|
|
|
|
case ALU_Ctrl.Oper is
|
|
when ALU_INC => -- Rn = Rn + 1 : Flags N,C,Z
|
|
Sum := ("0" & x"01") +
|
|
("0" & Regfile(Index));
|
|
Flags(FL_ZERO) <= nor_reduce(Sum(7 downto 0));
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Flags(FL_NEG) <= Sum(7);
|
|
Regfile(Index) <= Sum(7 downto 0);
|
|
|
|
when ALU_UPP => -- Rn = Rn + 1
|
|
Sum := ("0" & x"01") +
|
|
("0" & Regfile(Index));
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Regfile(Index) <= Sum(7 downto 0);
|
|
|
|
when ALU_UPP2 => -- Rn = Rn + C
|
|
Sum := ("0" & x"00") +
|
|
("0" & Regfile(Index)) +
|
|
Flags(FL_CARRY);
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Regfile(Index) <= Sum(7 downto 0);
|
|
|
|
when ALU_ADC => -- R0 = R0 + Rn + C : Flags N,C,Z
|
|
Sum := ("0" & Regfile(0)) +
|
|
("0" & Regfile(Index)) +
|
|
Flags(FL_CARRY);
|
|
Flags(FL_ZERO) <= nor_reduce(Sum(7 downto 0));
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Flags(FL_NEG) <= Sum(7);
|
|
Regfile(0) <= Sum(7 downto 0);
|
|
|
|
when ALU_TX0 => -- R0 = Rn : Flags N,Z
|
|
Temp := "0" & Regfile(Index);
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(0) <= Temp(7 downto 0);
|
|
|
|
when ALU_OR => -- R0 = R0 | Rn : Flags N,Z
|
|
Temp(7 downto 0) := Regfile(0) or Regfile(Index);
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(0) <= Temp(7 downto 0);
|
|
|
|
when ALU_AND => -- R0 = R0 & Rn : Flags N,Z
|
|
Temp(7 downto 0) := Regfile(0) and Regfile(Index);
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(0) <= Temp(7 downto 0);
|
|
|
|
when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z
|
|
Temp(7 downto 0) := Regfile(0) xor Regfile(Index);
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(0) <= Temp(7 downto 0);
|
|
|
|
when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z
|
|
Temp := Regfile(Index) & Flags(FL_CARRY);
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_CARRY) <= Temp(8);
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(Index) <= Temp(7 downto 0);
|
|
|
|
when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z
|
|
Temp := Regfile(Index)(0) & Flags(FL_CARRY) &
|
|
Regfile(Index)(7 downto 1);
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_CARRY) <= Temp(8);
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(Index) <= Temp(7 downto 0);
|
|
|
|
when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
|
|
Sum := ("0" & Regfile(Index)) +
|
|
("0" & x"FF");
|
|
Flags(FL_ZERO) <= nor_reduce(Sum(7 downto 0));
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Flags(FL_NEG) <= Sum(7);
|
|
Regfile(Index) <= Sum(7 downto 0);
|
|
|
|
when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
|
|
Sum := ("0" & Regfile(0)) +
|
|
("1" & (not Regfile(Index))) +
|
|
Flags(FL_CARRY);
|
|
Flags(FL_ZERO) <= nor_reduce(Sum(7 downto 0));
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Flags(FL_NEG) <= Sum(7);
|
|
Regfile(0) <= Sum(7 downto 0);
|
|
|
|
when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z
|
|
Sum := ("0" & Regfile(0)) +
|
|
("0" & Regfile(Index));
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Regfile(0) <= Sum(7 downto 0);
|
|
Flags(FL_ZERO) <= nor_reduce(Sum(7 downto 0));
|
|
Flags(FL_NEG) <= Sum(7);
|
|
|
|
when ALU_STP => -- Sets bit(n) in the Flags register
|
|
Flags(Index) <= '1';
|
|
|
|
when ALU_BTT => -- Z = !R0(N), N = R0(7)
|
|
Flags(FL_ZERO) <= not Regfile(0)(Index);
|
|
Flags(FL_NEG) <= Regfile(0)(7);
|
|
|
|
when ALU_CLP => -- Clears bit(n) in the Flags register
|
|
Flags(Index) <= '0';
|
|
|
|
when ALU_T0X => -- Rn = R0 : Flags N,Z
|
|
Temp := "0" & Regfile(0);
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(Index) <= Temp(7 downto 0);
|
|
|
|
when ALU_CMP => -- Sets Flags on R0 - Rn : Flags N,C,Z
|
|
Sum := ("0" & Regfile(0)) +
|
|
("1" & (not Regfile(Index))) +
|
|
'1';
|
|
Flags(FL_ZERO) <= nor_reduce(Sum(7 downto 0));
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Flags(FL_NEG) <= Sum(7);
|
|
|
|
when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
|
|
Regfile(0) <= Mult(7 downto 0);
|
|
Regfile(1) <= Mult(15 downto 8);
|
|
Flags(FL_ZERO) <= nor_reduce(Mult);
|
|
|
|
when ALU_LDI => -- Rn <= Data : Flags N,Z
|
|
Flags(FL_ZERO) <= nor_reduce(ALU_Ctrl.Data);
|
|
Flags(FL_NEG) <= ALU_Ctrl.Data(7);
|
|
Regfile(Index) <= ALU_Ctrl.Data;
|
|
|
|
when ALU_POP => -- Rn <= Data
|
|
Regfile(Index) <= ALU_Ctrl.Data;
|
|
|
|
when ALU_LDX => -- R0 <= Data : Flags N,Z
|
|
Flags(FL_ZERO) <= nor_reduce(ALU_Ctrl.Data);
|
|
Flags(FL_NEG) <= ALU_Ctrl.Data(7);
|
|
Regfile(0) <= ALU_Ctrl.Data;
|
|
|
|
when ALU_RFLG =>
|
|
Flags <= ALU_Ctrl.Data;
|
|
|
|
when others =>
|
|
null;
|
|
end case;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end architecture;
|
end architecture;
|
|
|
No newline at end of file
|
No newline at end of file
|
