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-- Copyright (c)2006, 2011, 2012, 2013, 2015, 2019 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL Units : o8_cpu
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-- Description: VHDL model of a RISC 8-bit processor core loosely based on the
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-- : V8/ARC uRISC instruction set. Requires Open8_pkg.vhd
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-- :
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-- Notes : Generic definitions
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-- :
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-- : Program_Start_Addr sets the initial value of the program
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-- : counter.
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-- :
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-- : ISR_Start_Addr sets the location of the interrupt service
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-- : vector table. There are 8 service vectors, or 16 bytes, which
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-- : must be allocated to either ROM or RAM.
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-- :
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-- : Stack_Start_Address sets the initial (reset) value of the
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-- : stack pointer. Also used for the RSP instruction if
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-- : Allow_Stack_Address_Move is false.
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-- :
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-- : Allow_Stack_Address_Move, when set true, allows the RSP to be
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-- : programmed via thet RSP instruction. If enabled, the
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-- : instruction changes into TSX or TXS based on the flag
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-- : specified by Stack_Xfer_Flag. If the flag is '0', RSP will
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-- : copy the current stack pointer to R1:R0 (TSX). If the flag
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-- : is '1', RSP will copy R1:R0 to the stack pointer (TXS). This
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-- : allows the processor to backup and restore stack pointers
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-- : in a multi-process environment. Note that no flags are
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-- : modified by either form of this instruction.
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-- :
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-- : Stack_Xfer_Flag instructs the core to use the specified ALU
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-- : flag to alter the behavior of the RSP instruction when
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-- : Allow_Stack_Address_Move is set TRUE, otherwise it is ignored.
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-- : While technically any of the status bits may be used, the
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-- : intent was to use FL_GP[1,2,3,4], as these are not modified
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-- : by ordinary ALU operations.
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-- :
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-- : The Enable_Auto_Increment generic can be used to modify the
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-- : indexed instructions such that specifying an odd register
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-- : will use the next lower register pair, post-incrementing the
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-- : value in that pair. IOW, specifying STX R1 will instead
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-- : result in STX R0++, or R0 = {R1:R0}; {R1:R0} + 1
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-- :
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-- : BRK_Implements_WAI modifies the BRK instruction such that it
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-- : triggers the wait for interrupt state, but without triggering
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-- : a soft interrupt in lieu of its normal behavior, which is to
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-- : insert several dead clock cycles - essentially a long NOP
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-- :
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-- : Enable_NMI overrides the mask bit for interrupt 0, creating a
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-- : non-maskable interrupt at the highest priority. To remain
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-- : true to the original core, this should be set false.
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-- :
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-- : Default_Interrupt_Mask sets the intial/reset value of the
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-- : interrupt mask. To remain true to the original core, which
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-- : had no interrupt mask, this should be set to x"FF". Otherwise
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-- : it can be initialized to any value. Note that Enable_NMI
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-- : will logically force the LSB high.
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-- :
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-- : Reset_Level determines whether the processor registers reset
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-- : on a high or low level from higher logic.
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-- :
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-- : Architecture notes
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-- : This model deviates from the original ISA in a few important
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-- : ways.
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-- :
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-- : First, there is only one set of registers. Interrupt service
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-- : routines must explicitely preserve context since the the
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-- : hardware doesn't. This was done to decrease size and code
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-- : complexity. Older code that assumes this behavior will not
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-- : execute correctly on this processor model.
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-- :
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-- : Second, this model adds an additional pipeline stage between
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-- : the instruction decoder and the ALU. Unfortunately, this
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-- : means that the instruction stream has to be restarted after
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-- : any math instruction is executed, implying that any ALU
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-- : instruction now has a latency of 2 instead of 0. The
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-- : advantage is that the maximum frequency has gone up
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-- : significantly, as the ALU code is vastly more efficient.
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-- : As an aside, this now means that all math instructions,
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-- : including MUL (see below) and UPP have the same instruction
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-- : latency.
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-- :
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-- : Third, the original ISA, also a soft core, had two reserved
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-- : instructions, USR and USR2. These have been implemented as
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-- : DBNZ, and MUL respectively.
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-- :
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-- : DBNZ decrements the specified register and branches if the
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-- : result is non-zero. The instruction effectively executes a
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-- : DEC Rn instruction prior to branching, so the same flags will
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-- : be set.
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-- :
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-- : MUL places the result of R0 * Rn into R1:R0. Instruction
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-- : latency is identical to other ALU instructions. Only the Z
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-- : flag is set, since there is no defined overflow or "negative
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-- : 16-bit values"
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-- :
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-- : Fourth, indexed load/store instructions now have an (optional)
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-- : ability to post-increment their index registers. If enabled,
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-- : using an odd operand for LDO,LDX, STO, STX will cause the
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-- : register pair to be incremented after the storage access.
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-- :
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-- : Fifth, the RSP instruction has been (optionally) altered to
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-- : allow the stack pointer to be sourced from R1:R0.
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-- :
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-- : Sixth, the BRK instruction can optionally implement a WAI,
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-- : which is the same as the INT instruction without the soft
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-- : interrupt, as a way to put the processor to "sleep" until the
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-- : next external interrupt.
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-- :
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-- : Seventh, the original CPU model had 8 non-maskable interrupts
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-- : with priority. This model has the same 8 interrupts, but
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-- : allows software to mask them (with an additional option to
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-- : override the highest priority interrupt, making it the NMI.)
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-- :
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-- : Lastly, previous unmapped instructions in the OP_STK opcode
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-- : were repurposed to support a new interrupt mask.
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-- : SMSK and GMSK transfer the contents of R0 (accumulator)
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-- : to/from the interrupt mask register. SMSK is immediate, while
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-- : GMSK has the same overhead as a math instruction.
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--
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-- Revision History
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 07/19/06 Design Start
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-- Seth Henry 01/18/11 Fixed BTT instruction to match V8
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-- Seth Henry 07/22/11 Fixed interrupt transition logic to avoid data
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-- corruption issues.
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-- Seth Henry 07/26/11 Optimized logic in ALU, stack pointer, and data
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-- path sections.
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-- Seth Henry 07/27/11 Optimized logic for timing, merged blocks into
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-- single entity.
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-- Seth Henry 09/20/11 Added BRK_Implements_WAI option, allowing the
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-- processor to wait for an interrupt instead of the
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-- normal BRK behavior.
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-- Seth Henry 12/20/11 Modified core to allow WAIT_FOR_INT state to idle
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-- the bus entirely (Rd_Enable is low)
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-- Seth Henry 02/03/12 Replaced complex interrupt controller with simpler,
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-- faster logic that simply does priority encoding.
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-- Seth Henry 08/06/13 Removed HALT functionality
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-- Seth Henry 10/29/15 Fixed inverted carry logic in CMP and SBC instrs
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-- Seth Henry 12/19/19 Renamed to o8_cpu to fit "theme"
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-- Seth Henry 03/09/20 Modified RSP instruction to work with a CPU flag
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-- allowing true backup/restore of the stack pointer
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-- Seth Henry 03/11/20 Split the address logic from the main state machine
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-- in order to simplify things and eliminate
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-- redundancies. Came across and fixed a problem with
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-- the STO instruction when Enable_Auto_Increment is
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-- NOT set.
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-- Seth Henry 03/11/20 Renamed core to "o8_cpu" to fit theme settled on
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-- over multiple projects.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
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library work;
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use work.Open8_pkg.all;
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entity o8_cpu is
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generic(
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Program_Start_Addr : ADDRESS_TYPE := x"0000"; -- Initial PC location
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ISR_Start_Addr : ADDRESS_TYPE := x"FFF0"; -- Bottom of ISR vec's
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Stack_Start_Addr : ADDRESS_TYPE := x"03FF"; -- Top of Stack
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Allow_Stack_Address_Move : boolean := false; -- Use Normal v8 RSP
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Stack_Xfer_Flag : integer := FL_GP1; -- If enabled, use GP1 to control RSP
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Enable_Auto_Increment : boolean := false; -- Modify indexed instr
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BRK_Implements_WAI : boolean := false; -- BRK -> Wait for Int
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Enable_NMI : boolean := true; -- Force INTR0 enabled
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Default_Interrupt_Mask : DATA_TYPE := x"FF"; -- Enable all Ints
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Reset_Level : std_logic := '0' ); -- Active reset level
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port(
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Clock : in std_logic;
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Reset : in std_logic;
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Interrupts : in INTERRUPT_BUNDLE;
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--
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Address : out ADDRESS_TYPE;
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Rd_Data : in DATA_TYPE;
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Rd_Enable : out std_logic;
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Wr_Data : out DATA_TYPE;
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Wr_Enable : out std_logic );
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end entity;
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architecture behave of o8_cpu is
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constant INT_VECTOR_0 : ADDRESS_TYPE := ISR_Start_Addr;
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constant INT_VECTOR_1 : ADDRESS_TYPE := ISR_Start_Addr+2;
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constant INT_VECTOR_2 : ADDRESS_TYPE := ISR_Start_Addr+4;
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constant INT_VECTOR_3 : ADDRESS_TYPE := ISR_Start_Addr+6;
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constant INT_VECTOR_4 : ADDRESS_TYPE := ISR_Start_Addr+8;
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constant INT_VECTOR_5 : ADDRESS_TYPE := ISR_Start_Addr+10;
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constant INT_VECTOR_6 : ADDRESS_TYPE := ISR_Start_Addr+12;
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constant INT_VECTOR_7 : ADDRESS_TYPE := ISR_Start_Addr+14;
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signal Halt : std_logic;
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signal CPU_Next_State : CPU_STATES := PIPE_FILL_0;
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signal CPU_State : CPU_STATES := PIPE_FILL_0;
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signal Cache_Ctrl : CACHE_MODES := CACHE_IDLE;
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signal Opcode : OPCODE_TYPE := (others => '0');
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signal SubOp, SubOp_p1 : SUBOP_TYPE := (others => '0');
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signal Prefetch : DATA_TYPE := x"00";
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signal Operand1, Operand2 : DATA_TYPE := x"00";
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signal Instr_Prefetch : std_logic := '0';
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signal PC_Ctrl : PC_CTRL_TYPE;
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signal Program_Ctr : ADDRESS_TYPE := x"0000";
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signal ALU_Ctrl : ALU_CTRL_TYPE;
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signal Regfile : REGFILE_TYPE;
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signal Flags : FLAG_TYPE;
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signal Mult : ADDRESS_TYPE := x"0000";
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signal SP_Ctrl : SP_CTRL_TYPE;
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signal Stack_Ptr : ADDRESS_TYPE := x"0000";
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signal DP_Ctrl : DATA_CTRL_TYPE;
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signal INT_Ctrl : INT_CTRL_TYPE;
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signal Ack_D, Ack_Q, Ack_Q1: std_logic := '0';
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signal Int_Req, Int_Ack : std_logic := '0';
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signal Int_Mask : DATA_TYPE := x"00";
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signal ISR_Addr : ADDRESS_TYPE := x"0000";
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signal i_Ints : INTERRUPT_BUNDLE := x"00";
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signal Pending : INTERRUPT_BUNDLE := x"00";
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signal Wait_for_FSM : std_logic := '0';
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begin
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-------------------------------------------------------------------------------
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-- Address bus selection/generation logic
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-------------------------------------------------------------------------------
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Address_Logic: process(CPU_State, Regfile, SubOp, SubOp_p1, Operand1, Operand2,
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Program_Ctr, Stack_Ptr, ISR_Addr )
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variable Reg, Reg_1 : integer range 0 to 7 := 0;
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variable Offset_SX : ADDRESS_TYPE;
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begin
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if( Enable_Auto_Increment )then
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Reg := conv_integer(SubOp(2 downto 1) & '0');
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Reg_1 := conv_integer(SubOp(2 downto 1) & '1');
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else
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Reg := conv_integer(SubOp);
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Reg_1 := conv_integer(SubOp_p1);
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end if;
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Offset_SX(15 downto 0) := (others => Operand1(7));
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Offset_SX(7 downto 0) := Operand1;
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case( CPU_State )is
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when LDA_C2 | STA_C2 =>
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Address <= Operand2 & Operand1;
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when LDX_C1 | STX_C1 =>
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Address <= (Regfile(Reg_1) & Regfile(Reg));
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when LDO_C1 | STO_C1 =>
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Address <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
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when ISR_C1 | ISR_C2 =>
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Address <= ISR_Addr;
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when PSH_C1 | POP_C1 | ISR_C3 | JSR_C1 | JSR_C2 | RTS_C1 | RTS_C2 | RTS_C3 =>
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Address <= Stack_Ptr;
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when others =>
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Address <= Program_Ctr;
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end case;
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end process;
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-------------------------------------------------------------------------------
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-- Combinatorial portion of CPU finite state machine
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-- State Logic / Instruction Decoding & Execution
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-------------------------------------------------------------------------------
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State_Logic: process(CPU_State, Flags, Int_Mask, Opcode,
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SubOp , SubOp_p1, Operand1, Operand2, Int_Req )
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variable Reg : integer range 0 to 7 := 0;
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begin
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CPU_Next_State <= CPU_State;
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Cache_Ctrl <= CACHE_IDLE;
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--
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PC_Ctrl.Oper <= PC_IDLE;
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PC_Ctrl.Offset <= x"03";
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PC_Ctrl.Addr <= x"0000";
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--
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ALU_Ctrl.Oper <= ALU_IDLE;
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ALU_Ctrl.Reg <= ACCUM;
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ALU_Ctrl.Data <= x"00";
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--
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SP_Ctrl.Oper <= SP_IDLE;
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--
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DP_Ctrl.Src <= DATA_RD_MEM;
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DP_Ctrl.Reg <= ACCUM;
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--
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INT_Ctrl.Mask_Set <= '0';
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INT_Ctrl.Soft_Ints <= x"00";
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INT_Ctrl.Incr_ISR <= '0';
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Ack_D <= '0';
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Reg := conv_integer(SubOp);
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case CPU_State is
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-------------------------------------------------------------------------------
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-- Initial Instruction fetch & decode
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-------------------------------------------------------------------------------
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when PIPE_FILL_0 =>
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CPU_Next_State <= PIPE_FILL_1;
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PC_Ctrl.Oper <= PC_INCR;
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when PIPE_FILL_1 =>
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CPU_Next_State <= PIPE_FILL_2;
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PC_Ctrl.Oper <= PC_INCR;
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when PIPE_FILL_2 =>
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CPU_Next_State <= INSTR_DECODE;
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Cache_Ctrl <= CACHE_INSTR;
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PC_Ctrl.Oper <= PC_INCR;
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when INSTR_DECODE =>
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CPU_Next_State <= INSTR_DECODE;
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Cache_Ctrl <= CACHE_INSTR;
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case Opcode is
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when OP_PSH =>
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CPU_Next_State <= PSH_C1;
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Cache_Ctrl <= CACHE_PREFETCH;
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PC_Ctrl.Oper <= PC_REV1;
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DP_Ctrl.Src <= DATA_WR_REG;
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DP_Ctrl.Reg <= SubOp;
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when OP_POP =>
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CPU_Next_State <= POP_C1;
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Cache_Ctrl <= CACHE_PREFETCH;
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PC_Ctrl.Oper <= PC_REV2;
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SP_Ctrl.Oper <= SP_POP;
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when OP_BR0 | OP_BR1 =>
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CPU_Next_State <= BRN_C1;
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Cache_Ctrl <= CACHE_OPER1;
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PC_Ctrl.Oper <= PC_INCR;
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when OP_DBNZ =>
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CPU_Next_State <= DBNZ_C1;
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Cache_Ctrl <= CACHE_OPER1;
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PC_Ctrl.Oper <= PC_INCR;
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ALU_Ctrl.Oper <= ALU_DEC;
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ALU_Ctrl.Reg <= SubOp;
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when OP_INT =>
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PC_Ctrl.Oper <= PC_INCR;
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-- Make sure the requested interrupt is actually enabled first
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if( Int_Mask(Reg) = '1' )then
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CPU_Next_State <= WAIT_FOR_INT;
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INT_Ctrl.Soft_Ints(Reg) <= '1';
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end if;
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when OP_STK =>
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case SubOp is
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when SOP_RSP =>
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PC_Ctrl.Oper <= PC_INCR;
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if( not Allow_Stack_Address_Move )then
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SP_Ctrl.Oper <= SP_CLR;
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end if;
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if( Allow_Stack_Address_Move and Flags(Stack_Xfer_Flag) = '1' )then
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SP_Ctrl.Oper <= SP_SET;
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end if;
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if( Allow_Stack_Address_Move and Flags(Stack_Xfer_Flag) = '0')then
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ALU_Ctrl.Oper <= ALU_TSX;
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end if;
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when SOP_RTS | SOP_RTI =>
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CPU_Next_State <= RTS_C1;
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Cache_Ctrl <= CACHE_IDLE;
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SP_Ctrl.Oper <= SP_POP;
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when SOP_BRK =>
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CPU_Next_State <= BRK_C1;
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PC_Ctrl.Oper <= PC_REV2;
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-- If Break implements Wait for Interrupt, replace the normal
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-- flow with a modified version of the INT instruction
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if( BRK_Implements_WAI )then
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CPU_Next_State <= WAIT_FOR_INT;
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PC_Ctrl.Oper <= PC_INCR;
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end if;
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when SOP_JMP =>
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CPU_Next_State <= JMP_C1;
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Cache_Ctrl <= CACHE_OPER1;
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when SOP_SMSK =>
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PC_Ctrl.Oper <= PC_INCR;
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INT_Ctrl.Mask_Set <= '1';
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when SOP_GMSK =>
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PC_Ctrl.Oper <= PC_INCR;
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ALU_Ctrl.Oper<= ALU_LDI;
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ALU_Ctrl.Reg <= ACCUM;
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ALU_Ctrl.Data<= Int_Mask;
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when SOP_JSR =>
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CPU_Next_State <= JSR_C1;
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Cache_Ctrl <= CACHE_OPER1;
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DP_Ctrl.Src <= DATA_WR_PC;
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DP_Ctrl.Reg <= PC_MSB;
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when others => null;
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end case;
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when OP_MUL =>
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CPU_Next_State <= MUL_C1;
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-- Multiplication requires a single clock cycle to calculate PRIOR
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-- to the ALU writing the result to registers. As a result, this
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-- state needs to idle the ALU initially, and back the PC up by 1
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-- We can get away with only 1 extra clock by pre-fetching the
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-- next instruction, though.
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Cache_Ctrl <= CACHE_PREFETCH;
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PC_Ctrl.Oper <= PC_REV1;
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-- Note that both the multiply process AND ALU process need the
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-- source register for Rn (R1:R0 = R0 * Rn). Assert ALU_Ctrl.reg
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-- now, but hold off on the ALU command until the next state.
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ALU_Ctrl.Oper <= ALU_IDLE;
|
|
ALU_Ctrl.Reg <= SubOp;
|
|
|
|
when OP_UPP =>
|
|
CPU_Next_State <= UPP_C1;
|
|
Cache_Ctrl <= CACHE_PREFETCH;
|
|
PC_Ctrl.Oper <= PC_REV1;
|
|
ALU_Ctrl.Oper <= Opcode;
|
|
ALU_Ctrl.Reg <= SubOp;
|
|
|
|
when OP_LDA =>
|
|
CPU_Next_State <= LDA_C1;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
|
|
|
when OP_LDI =>
|
|
CPU_Next_State <= LDI_C1;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
|
when OP_LDO =>
|
|
CPU_Next_State <= LDO_C1;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
|
PC_Ctrl.Oper <= PC_REV2;
|
|
|
|
when OP_LDX =>
|
|
CPU_Next_State <= LDX_C1;
|
|
Cache_Ctrl <= CACHE_PREFETCH;
|
|
PC_Ctrl.Oper <= PC_REV2;
|
|
|
|
when OP_STA =>
|
|
CPU_Next_State <= STA_C1;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
|
|
|
when OP_STO =>
|
|
CPU_Next_State <= STO_C1;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
|
PC_Ctrl.Oper <= PC_REV2;
|
|
DP_Ctrl.Src <= DATA_WR_REG;
|
|
DP_Ctrl.Reg <= ACCUM;
|
|
|
|
when OP_STX =>
|
|
CPU_Next_State <= STX_C1;
|
|
Cache_Ctrl <= CACHE_PREFETCH;
|
|
PC_Ctrl.Oper <= PC_REV2;
|
|
DP_Ctrl.Src <= DATA_WR_REG;
|
|
DP_Ctrl.Reg <= ACCUM;
|
|
|
|
when others =>
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= Opcode;
|
|
ALU_Ctrl.Reg <= SubOp;
|
|
|
|
end case;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Program Control (BR0_C1, BR1_C1, DBNZ_C1, JMP )
|
|
-------------------------------------------------------------------------------
|
|
|
|
when BRN_C1 =>
|
|
CPU_Next_State <= INSTR_DECODE;
|
|
Cache_Ctrl <= CACHE_INSTR;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
if( Flags(Reg) = Opcode(0) )then
|
|
CPU_Next_State <= PIPE_FILL_0;
|
|
Cache_Ctrl <= CACHE_IDLE;
|
|
PC_Ctrl.Offset <= Operand1;
|
|
end if;
|
|
|
|
when DBNZ_C1 =>
|
|
CPU_Next_State <= INSTR_DECODE;
|
|
Cache_Ctrl <= CACHE_INSTR;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
if( Flags(FL_ZERO) = '0' )then
|
|
CPU_Next_State <= PIPE_FILL_0;
|
|
Cache_Ctrl <= CACHE_IDLE;
|
|
PC_Ctrl.Offset <= Operand1;
|
|
end if;
|
|
|
|
when JMP_C1 =>
|
|
CPU_Next_State <= JMP_C2;
|
|
Cache_Ctrl <= CACHE_OPER2;
|
|
|
|
when JMP_C2 =>
|
|
CPU_Next_State <= PIPE_FILL_0;
|
|
PC_Ctrl.Oper <= PC_LOAD;
|
|
PC_Ctrl.Addr <= Operand2 & Operand1;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Data Storage - Load from memory (LDA, LDI, LDO, LDX)
|
|
-------------------------------------------------------------------------------
|
|
|
|
when LDA_C1 =>
|
|
CPU_Next_State <= LDA_C2;
|
|
Cache_Ctrl <= CACHE_OPER2;
|
|
|
|
when LDA_C2 =>
|
|
CPU_Next_State <= LDA_C3;
|
|
|
|
when LDA_C3 =>
|
|
CPU_Next_State <= LDA_C4;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
|
when LDA_C4 =>
|
|
CPU_Next_State <= LDI_C1;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
|
when LDI_C1 =>
|
|
CPU_Next_State <= INSTR_DECODE;
|
|
Cache_Ctrl <= CACHE_INSTR;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= ALU_LDI;
|
|
ALU_Ctrl.Reg <= SubOp;
|
|
ALU_Ctrl.Data <= Operand1;
|
|
|
|
when LDO_C1 =>
|
|
CPU_Next_State <= LDX_C2;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
if( Enable_Auto_Increment and SubOp(0) = '1' )then
|
|
ALU_Ctrl.Oper <= ALU_UPP;
|
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
|
end if;
|
|
|
|
when LDX_C1 =>
|
|
CPU_Next_State <= LDX_C2;
|
|
if( Enable_Auto_Increment and SubOp(0) = '1' )then
|
|
ALU_Ctrl.Oper <= ALU_UPP;
|
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
|
end if;
|
|
|
|
when LDX_C2 =>
|
|
CPU_Next_State <= LDX_C3;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
|
when LDX_C3 =>
|
|
CPU_Next_State <= LDX_C4;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
|
when LDX_C4 =>
|
|
CPU_Next_State <= INSTR_DECODE;
|
|
Cache_Ctrl <= CACHE_INSTR;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= ALU_LDI;
|
|
ALU_Ctrl.Reg <= ACCUM;
|
|
ALU_Ctrl.Data <= Operand1;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Data Storage - Store to memory (STA, STO, STX)
|
|
-------------------------------------------------------------------------------
|
|
when STA_C1 =>
|
|
CPU_Next_State <= STA_C2;
|
|
Cache_Ctrl <= CACHE_OPER2;
|
|
DP_Ctrl.Src <= DATA_WR_REG;
|
|
DP_Ctrl.Reg <= SubOp;
|
|
|
|
when STA_C2 =>
|
|
CPU_Next_State <= STA_C3;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
|
when STA_C3 =>
|
|
CPU_Next_State <= PIPE_FILL_2;
|
|
Cache_Ctrl <= CACHE_PREFETCH;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
|
when STO_C1 =>
|
|
CPU_Next_State <= PIPE_FILL_0;
|
|
Cache_Ctrl <= CACHE_PREFETCH;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
if( Enable_Auto_Increment and SubOp(0) = '1' )then
|
|
CPU_Next_State <= STO_C2;
|
|
ALU_Ctrl.Oper <= ALU_UPP;
|
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
|
end if;
|
|
|
|
when STO_C2 =>
|
|
CPU_Next_State <= PIPE_FILL_1;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= ALU_UPP2;
|
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '1';
|
|
|
|
when STX_C1 =>
|
|
CPU_Next_State <= PIPE_FILL_1;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
if( Enable_Auto_Increment and SubOp(0) = '1' )then
|
|
CPU_Next_State <= STX_C2;
|
|
ALU_Ctrl.Oper <= ALU_UPP;
|
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
|
end if;
|
|
|
|
when STX_C2 =>
|
|
CPU_Next_State <= PIPE_FILL_2;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= ALU_UPP2;
|
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '1';
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Multi-Cycle Math Operations (UPP, MUL)
|
|
-------------------------------------------------------------------------------
|
|
|
|
-- Because we have to backup the pipeline by 1 to refetch the 2nd
|
|
-- instruction/first operand, we have to return through PF2. Also, we
|
|
-- need to tell the ALU to store the results to R1:R0 here. Note that
|
|
-- there is no ALU_Ctrl.Reg, as this is implied in the ALU instruction
|
|
when MUL_C1 =>
|
|
CPU_Next_State <= PIPE_FILL_2;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= ALU_MUL;
|
|
|
|
when UPP_C1 =>
|
|
CPU_Next_State <= PIPE_FILL_2;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= ALU_UPP2;
|
|
ALU_Ctrl.Reg <= SubOp_p1;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Basic Stack Manipulation (PSH, POP, RSP)
|
|
-------------------------------------------------------------------------------
|
|
when PSH_C1 =>
|
|
CPU_Next_State <= PIPE_FILL_1;
|
|
SP_Ctrl.Oper <= SP_PUSH;
|
|
|
|
when POP_C1 =>
|
|
CPU_Next_State <= POP_C2;
|
|
|
|
when POP_C2 =>
|
|
CPU_Next_State <= POP_C3;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
|
when POP_C3 =>
|
|
CPU_Next_State <= POP_C4;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
|
|
when POP_C4 =>
|
|
CPU_Next_State <= INSTR_DECODE;
|
|
Cache_Ctrl <= CACHE_INSTR;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= ALU_POP;
|
|
ALU_Ctrl.Reg <= SubOp;
|
|
ALU_Ctrl.Data <= Operand1;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Subroutines & Interrupts (RTS, JSR)
|
|
-------------------------------------------------------------------------------
|
|
when WAIT_FOR_INT => -- For soft interrupts only, halt the Program_Ctr
|
|
CPU_Next_State <= WAIT_FOR_INT;
|
|
DP_Ctrl.Src <= DATA_BUS_IDLE;
|
|
|
|
when ISR_C1 =>
|
|
CPU_Next_State <= ISR_C2;
|
|
INT_Ctrl.Incr_ISR <= '1';
|
|
|
|
when ISR_C2 =>
|
|
CPU_Next_State <= ISR_C3;
|
|
DP_Ctrl.Src <= DATA_WR_FLAG;
|
|
|
|
when ISR_C3 =>
|
|
CPU_Next_State <= JSR_C1;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
|
ALU_Ctrl.Oper <= ALU_STP;
|
|
ALU_Ctrl.Reg <= INT_FLAG;
|
|
SP_Ctrl.Oper <= SP_PUSH;
|
|
DP_Ctrl.Src <= DATA_WR_PC;
|
|
DP_Ctrl.Reg <= PC_MSB;
|
|
Ack_D <= '1';
|
|
|
|
when JSR_C1 =>
|
|
CPU_Next_State <= JSR_C2;
|
|
Cache_Ctrl <= CACHE_OPER2;
|
|
SP_Ctrl.Oper <= SP_PUSH;
|
|
DP_Ctrl.Src <= DATA_WR_PC;
|
|
DP_Ctrl.Reg <= PC_LSB;
|
|
|
|
when JSR_C2 =>
|
|
CPU_Next_State <= PIPE_FILL_0;
|
|
PC_Ctrl.Oper <= PC_LOAD;
|
|
PC_Ctrl.Addr <= Operand2 & Operand1;
|
|
SP_Ctrl.Oper <= SP_PUSH;
|
|
|
|
when RTS_C1 =>
|
|
CPU_Next_State <= RTS_C2;
|
|
SP_Ctrl.Oper <= SP_POP;
|
|
|
|
when RTS_C2 =>
|
|
CPU_Next_State <= RTS_C3;
|
|
-- if this is an RTI, then we need to POP the flags
|
|
if( SubOp = SOP_RTI )then
|
|
SP_Ctrl.Oper <= SP_POP;
|
|
end if;
|
|
|
|
when RTS_C3 =>
|
|
CPU_Next_State <= RTS_C4;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
|
|
|
when RTS_C4 =>
|
|
CPU_Next_State <= RTS_C5;
|
|
Cache_Ctrl <= CACHE_OPER2;
|
|
|
|
when RTS_C5 =>
|
|
CPU_Next_State <= PIPE_FILL_0;
|
|
PC_Ctrl.Oper <= PC_LOAD;
|
|
PC_Ctrl.Addr <= Operand2 & Operand1;
|
|
if( SubOp = SOP_RTI )then
|
|
CPU_Next_State <= RTI_C6;
|
|
Cache_Ctrl <= CACHE_OPER1;
|
|
end if;
|
|
|
|
when RTI_C6 =>
|
|
CPU_Next_State <= PIPE_FILL_1;
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
ALU_Ctrl.Oper <= ALU_RFLG;
|
|
ALU_Ctrl.Data <= Operand1;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Debugging (BRK) Performs a 5-clock NOP
|
|
-------------------------------------------------------------------------------
|
|
when BRK_C1 =>
|
|
CPU_Next_State <= PIPE_FILL_0;
|
|
|
|
when others =>
|
|
null;
|
|
end case;
|
|
|
|
-- Interrupt service routines can only begin during the decode and wait
|
|
-- states to avoid corruption due to incomplete instruction execution
|
|
if( Int_Req = '1' )then
|
|
if( CPU_State = INSTR_DECODE or CPU_State = WAIT_FOR_INT )then
|
|
CPU_Next_State <= ISR_C1;
|
|
Cache_Ctrl <= CACHE_IDLE;
|
|
-- Rewind the PC by 3 to compensate for the pipeline registers
|
|
PC_Ctrl.Oper <= PC_INCR;
|
|
PC_Ctrl.Offset <= x"FF";
|
|
-- Reset all of the sub-block controls to IDLE, to avoid unintended
|
|
-- operation due to the current instruction
|
|
ALU_Ctrl.Oper <= ALU_IDLE;
|
|
SP_Ctrl.Oper <= SP_IDLE;
|
|
DP_Ctrl.Src <= DATA_RD_MEM;
|
|
INT_Ctrl.Soft_Ints <= (others => '0');
|
|
|
|
end if;
|
|
end if;
|
|
|
|
end process;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Registered portion of CPU finite state machine
|
|
-------------------------------------------------------------------------------
|
|
|
|
CPU_Regs: process( Reset, Clock )
|
|
variable Offset_SX : ADDRESS_TYPE;
|
|
variable i_Ints : INTERRUPT_BUNDLE := (others => '0');
|
|
variable Index : integer range 0 to 7 := 0;
|
|
variable Sum : std_logic_vector(8 downto 0) := "000000000";
|
|
variable Temp : std_logic_vector(8 downto 0) := "000000000";
|
|
begin
|
|
if( Reset = Reset_Level )then
|
|
CPU_State <= PIPE_FILL_0;
|
|
Opcode <= OP_INC;
|
|
SubOp <= ACCUM;
|
|
SubOp_p1 <= ACCUM;
|
|
Operand1 <= x"00";
|
|
Operand2 <= x"00";
|
|
Instr_Prefetch <= '0';
|
|
Prefetch <= x"00";
|
|
|
|
Wr_Data <= (others => '0');
|
|
Wr_Enable <= '0';
|
|
Rd_Enable <= '1';
|
|
|
|
Program_Ctr <= Program_Start_Addr;
|
|
Stack_Ptr <= Stack_Start_Addr;
|
|
|
|
Ack_Q <= '0';
|
|
Ack_Q1 <= '0';
|
|
Int_Ack <= '0';
|
|
|
|
Int_Req <= '0';
|
|
Pending <= x"00";
|
|
Wait_for_FSM <= '0';
|
|
if( Enable_NMI )then
|
|
Int_Mask <= Default_Interrupt_Mask(7 downto 1) & '1';
|
|
else
|
|
Int_Mask <= Default_Interrupt_Mask;
|
|
end if;
|
|
ISR_Addr <= INT_VECTOR_0;
|
|
|
|
for i in 0 to 7 loop
|
|
Regfile(i) <= (others => '0');
|
|
end loop;
|
|
Flags <= x"00";
|
|
|
|
elsif( rising_edge(Clock) )then
|
|
Wr_Enable <= '0';
|
|
Wr_Data <= x"00";
|
|
Rd_Enable <= '0';
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Instruction/Operand caching for pipelined memory access
|
|
-------------------------------------------------------------------------------
|
|
CPU_State <= CPU_Next_State;
|
|
case Cache_Ctrl is
|
|
when CACHE_INSTR =>
|
|
Opcode <= Rd_Data(7 downto 3);
|
|
SubOp <= Rd_Data(2 downto 0);
|
|
SubOp_p1 <= Rd_Data(2 downto 0) + 1;
|
|
if( Instr_Prefetch = '1' )then
|
|
Opcode <= Prefetch(7 downto 3);
|
|
SubOp <= Prefetch(2 downto 0);
|
|
SubOp_p1 <= Prefetch(2 downto 0) + 1;
|
|
Instr_Prefetch <= '0';
|
|
end if;
|
|
|
|
when CACHE_OPER1 =>
|
|
Operand1 <= Rd_Data;
|
|
|
|
when CACHE_OPER2 =>
|
|
Operand2 <= Rd_Data;
|
|
|
|
when CACHE_PREFETCH =>
|
|
Prefetch <= Rd_Data;
|
|
Instr_Prefetch <= '1';
|
|
|
|
when CACHE_IDLE =>
|
|
null;
|
|
end case;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Program Counter
|
|
-------------------------------------------------------------------------------
|
|
Offset_SX(15 downto 8) := (others => PC_Ctrl.Offset(7));
|
|
Offset_SX(7 downto 0) := PC_Ctrl.Offset;
|
|
|
|
case PC_Ctrl.Oper is
|
|
when PC_IDLE =>
|
|
null;
|
|
|
|
when PC_REV1 =>
|
|
Program_Ctr <= Program_Ctr - 1;
|
|
|
|
when PC_REV2 =>
|
|
Program_Ctr <= Program_Ctr - 2;
|
|
|
|
when PC_INCR =>
|
|
Program_Ctr <= Program_Ctr + Offset_SX - 2;
|
|
|
|
when PC_LOAD =>
|
|
Program_Ctr <= PC_Ctrl.Addr;
|
|
|
|
when others =>
|
|
null;
|
|
end case;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- (Write) Data Path
|
|
-------------------------------------------------------------------------------
|
|
case DP_Ctrl.Src is
|
|
when DATA_BUS_IDLE =>
|
|
null;
|
|
|
|
when DATA_RD_MEM =>
|
|
Rd_Enable <= '1';
|
|
|
|
when DATA_WR_REG =>
|
|
Wr_Enable <= '1';
|
|
Wr_Data <= Regfile(conv_integer(DP_Ctrl.Reg));
|
|
|
|
when DATA_WR_FLAG =>
|
|
Wr_Enable <= '1';
|
|
Wr_Data <= Flags;
|
|
|
|
when DATA_WR_PC =>
|
|
Wr_Enable <= '1';
|
|
Wr_Data <= Program_Ctr(15 downto 8);
|
|
if( DP_Ctrl.Reg = PC_LSB )then
|
|
Wr_Data <= Program_Ctr(7 downto 0);
|
|
end if;
|
|
|
|
when others =>
|
|
null;
|
|
end case;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Stack Pointer
|
|
-------------------------------------------------------------------------------
|
|
case SP_Ctrl.Oper is
|
|
when SP_IDLE =>
|
|
null;
|
|
|
|
when SP_CLR =>
|
|
Stack_Ptr <= Stack_Start_Addr;
|
|
|
|
when SP_SET =>
|
|
Stack_Ptr <= Regfile(1) & Regfile(0);
|
|
|
|
when SP_POP =>
|
|
Stack_Ptr <= Stack_Ptr + 1;
|
|
|
|
when SP_PUSH =>
|
|
Stack_Ptr <= Stack_Ptr - 1;
|
|
|
|
when others =>
|
|
null;
|
|
|
|
end case;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Interrupt Controller
|
|
-------------------------------------------------------------------------------
|
|
-- The interrupt control mask is always sourced out of R0
|
|
if( INT_Ctrl.Mask_Set = '1' )then
|
|
if( Enable_NMI )then
|
|
Int_Mask <= Regfile(conv_integer(ACCUM))(7 downto 1) & '1';
|
|
else
|
|
Int_Mask <= Regfile(conv_integer(ACCUM));
|
|
end if;
|
|
end if;
|
|
|
|
-- Combine external and internal interrupts, and mask the OR of the two
|
|
-- with the mask. Record any incoming interrupts to the pending buffer
|
|
i_Ints := (Interrupts or INT_Ctrl.Soft_Ints) and
|
|
Int_Mask;
|
|
|
|
Pending <= i_Ints or Pending;
|
|
|
|
if( Wait_for_FSM = '0' )then
|
|
if( Pending(0) = '1' )then
|
|
ISR_Addr <= INT_VECTOR_0;
|
|
Pending(0) <= '0';
|
|
Wait_for_FSM <= '1';
|
|
elsif( Pending(1) = '1' )then
|
|
ISR_Addr <= INT_VECTOR_1;
|
|
Pending(1) <= '0';
|
|
Wait_for_FSM <= '1';
|
|
elsif( Pending(2) = '1' )then
|
|
ISR_Addr <= INT_VECTOR_2;
|
|
Pending(2) <= '0';
|
|
Wait_for_FSM <= '1';
|
|
elsif( Pending(3) = '1' )then
|
|
ISR_Addr <= INT_VECTOR_3;
|
|
Pending(3) <= '0';
|
|
Wait_for_FSM <= '1';
|
|
elsif( Pending(4) = '1' )then
|
|
ISR_Addr <= INT_VECTOR_4;
|
|
Pending(4) <= '0';
|
|
Wait_for_FSM <= '1';
|
|
elsif( Pending(5) = '1' )then
|
|
ISR_Addr <= INT_VECTOR_5;
|
|
Pending(5) <= '0';
|
|
Wait_for_FSM <= '1';
|
|
elsif( Pending(6) = '1' )then
|
|
ISR_Addr <= INT_VECTOR_6;
|
|
Pending(6) <= '0';
|
|
Wait_for_FSM <= '1';
|
|
elsif( Pending(7) = '1' )then
|
|
ISR_Addr <= INT_VECTOR_7;
|
|
Pending(7) <= '0';
|
|
Wait_for_FSM <= '1';
|
|
end if;
|
|
end if;
|
|
|
|
-- Reset the Wait_for_FSM flag on Int_Ack
|
|
Ack_Q <= Ack_D;
|
|
Ack_Q1 <= Ack_Q;
|
|
Int_Ack <= Ack_Q1;
|
|
if( Int_Ack = '1' )then
|
|
Wait_for_FSM <= '0';
|
|
end if;
|
|
|
|
Int_Req <= Wait_for_FSM and (not Int_Ack);
|
|
|
|
-- Incr_ISR allows the CPU Core to advance the vector address to pop the
|
|
-- lower half of the address.
|
|
if( INT_Ctrl.Incr_ISR = '1' )then
|
|
ISR_Addr <= ISR_Addr + 1;
|
|
end if;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- ALU (Arithmetic / Logic Unit)
|
|
-------------------------------------------------------------------------------
|
|
Index := conv_integer(ALU_Ctrl.Reg);
|
|
Sum := (others => '0');
|
|
Temp := (others => '0');
|
|
|
|
case ALU_Ctrl.Oper is
|
|
when ALU_INC => -- Rn = Rn + 1 : Flags N,C,Z
|
|
Sum := ("0" & x"01") +
|
|
("0" & Regfile(Index));
|
|
Flags(FL_ZERO) <= nor_reduce(Sum(7 downto 0));
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Flags(FL_NEG) <= Sum(7);
|
|
Regfile(Index) <= Sum(7 downto 0);
|
|
|
|
when ALU_UPP => -- Rn = Rn + 1
|
|
Sum := ("0" & x"01") +
|
|
("0" & Regfile(Index));
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Regfile(Index) <= Sum(7 downto 0);
|
|
|
|
when ALU_UPP2 => -- Rn = Rn + C
|
|
Sum := ("0" & x"00") +
|
|
("0" & Regfile(Index)) +
|
|
Flags(FL_CARRY);
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Regfile(Index) <= Sum(7 downto 0);
|
|
|
|
when ALU_ADC => -- R0 = R0 + Rn + C : Flags N,C,Z
|
|
Sum := ("0" & Regfile(0)) +
|
|
("0" & Regfile(Index)) +
|
|
Flags(FL_CARRY);
|
|
Flags(FL_ZERO) <= nor_reduce(Sum(7 downto 0));
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Flags(FL_NEG) <= Sum(7);
|
|
Regfile(0) <= Sum(7 downto 0);
|
|
|
|
when ALU_TX0 => -- R0 = Rn : Flags N,Z
|
|
Temp := "0" & Regfile(Index);
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(0) <= Temp(7 downto 0);
|
|
|
|
when ALU_OR => -- R0 = R0 | Rn : Flags N,Z
|
|
Temp(7 downto 0) := Regfile(0) or Regfile(Index);
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(0) <= Temp(7 downto 0);
|
|
|
|
when ALU_AND => -- R0 = R0 & Rn : Flags N,Z
|
|
Temp(7 downto 0) := Regfile(0) and Regfile(Index);
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(0) <= Temp(7 downto 0);
|
|
|
|
when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z
|
|
Temp(7 downto 0) := Regfile(0) xor Regfile(Index);
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(0) <= Temp(7 downto 0);
|
|
|
|
when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z
|
|
Temp := Regfile(Index) & Flags(FL_CARRY);
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_CARRY) <= Temp(8);
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(Index) <= Temp(7 downto 0);
|
|
|
|
when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z
|
|
Temp := Regfile(Index)(0) & Flags(FL_CARRY) &
|
|
Regfile(Index)(7 downto 1);
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_CARRY) <= Temp(8);
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(Index) <= Temp(7 downto 0);
|
|
|
|
when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
|
|
Sum := ("0" & Regfile(Index)) +
|
|
("0" & x"FF");
|
|
Flags(FL_ZERO) <= nor_reduce(Sum(7 downto 0));
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Flags(FL_NEG) <= Sum(7);
|
|
Regfile(Index) <= Sum(7 downto 0);
|
|
|
|
when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
|
|
Sum := ("0" & Regfile(0)) +
|
|
("1" & (not Regfile(Index))) +
|
|
Flags(FL_CARRY);
|
|
Flags(FL_ZERO) <= nor_reduce(Sum(7 downto 0));
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Flags(FL_NEG) <= Sum(7);
|
|
Regfile(0) <= Sum(7 downto 0);
|
|
|
|
when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z
|
|
Sum := ("0" & Regfile(0)) +
|
|
("0" & Regfile(Index));
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Regfile(0) <= Sum(7 downto 0);
|
|
Flags(FL_ZERO) <= nor_reduce(Sum(7 downto 0));
|
|
Flags(FL_NEG) <= Sum(7);
|
|
|
|
when ALU_STP => -- Sets bit(n) in the Flags register
|
|
Flags(Index) <= '1';
|
|
|
|
when ALU_BTT => -- Z = !R0(N), N = R0(7)
|
|
Flags(FL_ZERO) <= not Regfile(0)(Index);
|
|
Flags(FL_NEG) <= Regfile(0)(7);
|
|
|
|
when ALU_CLP => -- Clears bit(n) in the Flags register
|
|
Flags(Index) <= '0';
|
|
|
|
when ALU_T0X => -- Rn = R0 : Flags N,Z
|
|
Temp := "0" & Regfile(0);
|
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
|
Flags(FL_NEG) <= Temp(7);
|
|
Regfile(Index) <= Temp(7 downto 0);
|
|
|
|
when ALU_CMP => -- Sets Flags on R0 - Rn : Flags N,C,Z
|
|
Sum := ("0" & Regfile(0)) +
|
|
("1" & (not Regfile(Index))) +
|
|
'1';
|
|
Flags(FL_ZERO) <= nor_reduce(Sum(7 downto 0));
|
|
Flags(FL_CARRY) <= Sum(8);
|
|
Flags(FL_NEG) <= Sum(7);
|
|
|
|
when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
|
|
Regfile(0) <= Mult(7 downto 0);
|
|
Regfile(1) <= Mult(15 downto 8);
|
|
Flags(FL_ZERO) <= nor_reduce(Mult);
|
|
|
|
when ALU_LDI => -- Rn <= Data : Flags N,Z
|
|
Flags(FL_ZERO) <= nor_reduce(ALU_Ctrl.Data);
|
|
Flags(FL_NEG) <= ALU_Ctrl.Data(7);
|
|
Regfile(Index) <= ALU_Ctrl.Data;
|
|
|
|
when ALU_POP => -- Rn <= Data
|
|
Regfile(Index) <= ALU_Ctrl.Data;
|
|
|
|
when ALU_RFLG =>
|
|
Flags <= ALU_Ctrl.Data;
|
|
|
|
when ALU_TSX =>
|
|
Regfile(0) <= Stack_Ptr(7 downto 0);
|
|
Regfile(1) <= Stack_Ptr(15 downto 8);
|
|
|
|
when others =>
|
|
null;
|
|
end case;
|
|
|
|
end if;
|
|
end process;
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- Multiplier Logic
|
|
--
|
|
-- We need to infer a hardware multipler, so we create a special clocked
|
|
-- process with no reset or clock enable
|
|
-------------------------------------------------------------------------------
|
|
|
|
Multiplier_proc: process( Clock )
|
|
begin
|
|
if( rising_edge(Clock) )then
|
|
Mult <= Regfile(0) *
|
|
Regfile(conv_integer(ALU_Ctrl.Reg));
|
|
end if;
|
|
end process;
|
|
|
|
end architecture;
|
|
|
No newline at end of file
|
No newline at end of file
|
