| Line 1... |
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-- Copyright (c)2006, 2011, 2012, 2013, 2015, 2019 Jeremy Seth Henry
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-- Copyright (c)2006, 2011, 2012, 2013, 2015, 2019, 2020 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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| Line 164... |
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-- Seth Henry 03/11/20 Split the address logic from the main state machine
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-- Seth Henry 03/11/20 Split the address logic from the main state machine
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-- in order to simplify things and eliminate
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-- in order to simplify things and eliminate
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-- redundancies. Came across and fixed a problem with
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-- redundancies. Came across and fixed a problem with
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-- the STO instruction when Enable_Auto_Increment is
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-- the STO instruction when Enable_Auto_Increment is
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-- NOT set.
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-- NOT set.
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-- Seth Henry 03/11/20 Renamed core to "o8_cpu" to fit theme settled on
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-- Seth Henry 03/12/20 Rationalized the naming of the CPU flags to match
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-- over multiple projects.
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-- the assembler names. Also fixed an issue where
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-- the I bit wasn't being cleared after interrupts.
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-- Simplified the program counter logic to only use
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-- the offset for increments, redefining the
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-- original modes as fixed offset values.
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-- Modified the ALU section with a new ALU operation
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-- for GMSK. This allowed the .data field to be
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-- removed and Operand1 used in its place, which
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-- simplified the logic a great deal.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 182... |
Line 190... |
generic(
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generic(
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Program_Start_Addr : ADDRESS_TYPE := x"0000"; -- Initial PC location
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Program_Start_Addr : ADDRESS_TYPE := x"0000"; -- Initial PC location
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ISR_Start_Addr : ADDRESS_TYPE := x"FFF0"; -- Bottom of ISR vec's
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ISR_Start_Addr : ADDRESS_TYPE := x"FFF0"; -- Bottom of ISR vec's
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Stack_Start_Addr : ADDRESS_TYPE := x"03FF"; -- Top of Stack
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Stack_Start_Addr : ADDRESS_TYPE := x"03FF"; -- Top of Stack
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Allow_Stack_Address_Move : boolean := false; -- Use Normal v8 RSP
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Allow_Stack_Address_Move : boolean := false; -- Use Normal v8 RSP
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Stack_Xfer_Flag : integer := FL_GP1; -- If enabled, use GP1 to control RSP
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Stack_Xfer_Flag : integer := PSR_GP4; -- If enabled, use GP4 to control RSP
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Enable_Auto_Increment : boolean := false; -- Modify indexed instr
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Enable_Auto_Increment : boolean := false; -- Modify indexed instr
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BRK_Implements_WAI : boolean := false; -- BRK -> Wait for Int
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BRK_Implements_WAI : boolean := false; -- BRK -> Wait for Int
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Enable_NMI : boolean := true; -- Force INTR0 enabled
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Enable_NMI : boolean := true; -- Force INTR0 enabled
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Default_Interrupt_Mask : DATA_TYPE := x"FF"; -- Enable all Ints
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Default_Interrupt_Mask : DATA_TYPE := x"FF"; -- Enable all Ints
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Reset_Level : std_logic := '0' ); -- Active reset level
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Reset_Level : std_logic := '0' ); -- Active reset level
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| Line 211... |
Line 219... |
constant INT_VECTOR_4 : ADDRESS_TYPE := ISR_Start_Addr+8;
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constant INT_VECTOR_4 : ADDRESS_TYPE := ISR_Start_Addr+8;
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constant INT_VECTOR_5 : ADDRESS_TYPE := ISR_Start_Addr+10;
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constant INT_VECTOR_5 : ADDRESS_TYPE := ISR_Start_Addr+10;
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constant INT_VECTOR_6 : ADDRESS_TYPE := ISR_Start_Addr+12;
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constant INT_VECTOR_6 : ADDRESS_TYPE := ISR_Start_Addr+12;
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constant INT_VECTOR_7 : ADDRESS_TYPE := ISR_Start_Addr+14;
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constant INT_VECTOR_7 : ADDRESS_TYPE := ISR_Start_Addr+14;
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signal Halt : std_logic;
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signal CPU_Next_State : CPU_STATES := PIPE_FILL_0;
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signal CPU_Next_State : CPU_STATES := PIPE_FILL_0;
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signal CPU_State : CPU_STATES := PIPE_FILL_0;
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signal CPU_State : CPU_STATES := PIPE_FILL_0;
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signal Cache_Ctrl : CACHE_MODES := CACHE_IDLE;
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signal Cache_Ctrl : CACHE_MODES := CACHE_IDLE;
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| Line 250... |
Line 256... |
signal Pending : INTERRUPT_BUNDLE := x"00";
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signal Pending : INTERRUPT_BUNDLE := x"00";
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signal Wait_for_FSM : std_logic := '0';
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signal Wait_for_FSM : std_logic := '0';
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begin
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begin
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Address bus selection/generation logic
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-- Address bus selection/generation logic
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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Address_Logic: process(CPU_State, Regfile, SubOp, SubOp_p1, Operand1, Operand2,
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Address_Logic: process(CPU_State, Regfile, SubOp, SubOp_p1, Operand1,
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Program_Ctr, Stack_Ptr, ISR_Addr )
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Operand2, Program_Ctr, Stack_Ptr, ISR_Addr )
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variable Reg, Reg_1 : integer range 0 to 7 := 0;
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variable Reg, Reg_1 : integer range 0 to 7 := 0;
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variable Offset_SX : ADDRESS_TYPE;
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variable Offset_SX : ADDRESS_TYPE;
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begin
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begin
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if( Enable_Auto_Increment )then
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if( Enable_Auto_Increment )then
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| Line 307... |
Line 314... |
variable Reg : integer range 0 to 7 := 0;
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variable Reg : integer range 0 to 7 := 0;
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begin
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begin
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CPU_Next_State <= CPU_State;
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CPU_Next_State <= CPU_State;
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Cache_Ctrl <= CACHE_IDLE;
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Cache_Ctrl <= CACHE_IDLE;
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--
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--
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PC_Ctrl.Oper <= PC_IDLE;
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PC_Ctrl.Oper <= PC_INCR;
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PC_Ctrl.Offset <= x"03";
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PC_Ctrl.Offset <= PC_IDLE;
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PC_Ctrl.Addr <= x"0000";
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--
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--
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ALU_Ctrl.Oper <= ALU_IDLE;
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ALU_Ctrl.Oper <= ALU_IDLE;
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ALU_Ctrl.Reg <= ACCUM;
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ALU_Ctrl.Reg <= ACCUM;
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ALU_Ctrl.Data <= x"00";
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--
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--
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SP_Ctrl.Oper <= SP_IDLE;
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SP_Ctrl.Oper <= SP_IDLE;
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--
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--
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DP_Ctrl.Src <= DATA_RD_MEM;
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DP_Ctrl.Src <= DATA_RD_MEM;
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DP_Ctrl.Reg <= ACCUM;
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DP_Ctrl.Reg <= ACCUM;
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| Line 333... |
Line 338... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Initial Instruction fetch & decode
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-- Initial Instruction fetch & decode
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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when PIPE_FILL_0 =>
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when PIPE_FILL_0 =>
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CPU_Next_State <= PIPE_FILL_1;
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CPU_Next_State <= PIPE_FILL_1;
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PC_Ctrl.Oper <= PC_INCR;
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PC_Ctrl.Offset <= PC_NEXT;
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when PIPE_FILL_1 =>
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when PIPE_FILL_1 =>
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CPU_Next_State <= PIPE_FILL_2;
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CPU_Next_State <= PIPE_FILL_2;
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PC_Ctrl.Oper <= PC_INCR;
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PC_Ctrl.Offset <= PC_NEXT;
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when PIPE_FILL_2 =>
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when PIPE_FILL_2 =>
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CPU_Next_State <= INSTR_DECODE;
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CPU_Next_State <= INSTR_DECODE;
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Cache_Ctrl <= CACHE_INSTR;
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Cache_Ctrl <= CACHE_INSTR;
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PC_Ctrl.Oper <= PC_INCR;
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PC_Ctrl.Offset <= PC_NEXT;
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when INSTR_DECODE =>
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when INSTR_DECODE =>
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CPU_Next_State <= INSTR_DECODE;
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CPU_Next_State <= INSTR_DECODE;
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Cache_Ctrl <= CACHE_INSTR;
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Cache_Ctrl <= CACHE_INSTR;
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case Opcode is
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case Opcode is
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when OP_PSH =>
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when OP_PSH =>
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CPU_Next_State <= PSH_C1;
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CPU_Next_State <= PSH_C1;
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Cache_Ctrl <= CACHE_PREFETCH;
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Cache_Ctrl <= CACHE_PREFETCH;
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PC_Ctrl.Oper <= PC_REV1;
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PC_Ctrl.Offset <= PC_REV1;
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DP_Ctrl.Src <= DATA_WR_REG;
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DP_Ctrl.Src <= DATA_WR_REG;
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DP_Ctrl.Reg <= SubOp;
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DP_Ctrl.Reg <= SubOp;
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when OP_POP =>
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when OP_POP =>
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CPU_Next_State <= POP_C1;
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CPU_Next_State <= POP_C1;
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Cache_Ctrl <= CACHE_PREFETCH;
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Cache_Ctrl <= CACHE_PREFETCH;
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PC_Ctrl.Oper <= PC_REV2;
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PC_Ctrl.Offset <= PC_REV2;
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SP_Ctrl.Oper <= SP_POP;
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SP_Ctrl.Oper <= SP_POP;
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when OP_BR0 | OP_BR1 =>
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when OP_BR0 | OP_BR1 =>
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CPU_Next_State <= BRN_C1;
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CPU_Next_State <= BRN_C1;
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Cache_Ctrl <= CACHE_OPER1;
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Cache_Ctrl <= CACHE_OPER1;
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PC_Ctrl.Oper <= PC_INCR;
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PC_Ctrl.Offset <= PC_NEXT;
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when OP_DBNZ =>
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when OP_DBNZ =>
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CPU_Next_State <= DBNZ_C1;
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CPU_Next_State <= DBNZ_C1;
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Cache_Ctrl <= CACHE_OPER1;
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Cache_Ctrl <= CACHE_OPER1;
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PC_Ctrl.Oper <= PC_INCR;
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PC_Ctrl.Offset <= PC_NEXT;
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ALU_Ctrl.Oper <= ALU_DEC;
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ALU_Ctrl.Oper <= ALU_DEC;
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ALU_Ctrl.Reg <= SubOp;
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ALU_Ctrl.Reg <= SubOp;
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when OP_INT =>
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when OP_INT =>
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PC_Ctrl.Oper <= PC_INCR;
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PC_Ctrl.Offset <= PC_NEXT;
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-- Make sure the requested interrupt is actually enabled first
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-- Make sure the requested interrupt is actually enabled first
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if( Int_Mask(Reg) = '1' )then
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if( Int_Mask(Reg) = '1' )then
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CPU_Next_State <= WAIT_FOR_INT;
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CPU_Next_State <= WAIT_FOR_INT;
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INT_Ctrl.Soft_Ints(Reg) <= '1';
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INT_Ctrl.Soft_Ints(Reg) <= '1';
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end if;
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end if;
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when OP_STK =>
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when OP_STK =>
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case SubOp is
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case SubOp is
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when SOP_RSP =>
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when SOP_RSP =>
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PC_Ctrl.Oper <= PC_INCR;
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PC_Ctrl.Offset <= PC_NEXT;
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if( not Allow_Stack_Address_Move )then
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if( not Allow_Stack_Address_Move )then
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SP_Ctrl.Oper <= SP_CLR;
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SP_Ctrl.Oper <= SP_CLR;
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end if;
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end if;
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if( Allow_Stack_Address_Move and Flags(Stack_Xfer_Flag) = '1' )then
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if( Allow_Stack_Address_Move and Flags(Stack_Xfer_Flag) = '1' )then
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SP_Ctrl.Oper <= SP_SET;
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SP_Ctrl.Oper <= SP_SET;
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end if;
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end if;
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if( Allow_Stack_Address_Move and Flags(Stack_Xfer_Flag) = '0')then
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if( Allow_Stack_Address_Move and Flags(Stack_Xfer_Flag) = '0')then
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ALU_Ctrl.Oper <= ALU_TSX;
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ALU_Ctrl.Oper <= ALU_RSP;
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end if;
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end if;
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when SOP_RTS | SOP_RTI =>
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when SOP_RTS | SOP_RTI =>
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CPU_Next_State <= RTS_C1;
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CPU_Next_State <= RTS_C1;
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Cache_Ctrl <= CACHE_IDLE;
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Cache_Ctrl <= CACHE_IDLE;
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SP_Ctrl.Oper <= SP_POP;
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SP_Ctrl.Oper <= SP_POP;
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when SOP_BRK =>
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when SOP_BRK =>
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CPU_Next_State <= BRK_C1;
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CPU_Next_State <= BRK_C1;
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PC_Ctrl.Oper <= PC_REV2;
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PC_Ctrl.Offset <= PC_REV2;
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-- If Break implements Wait for Interrupt, replace the normal
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-- If Break implements Wait for Interrupt, replace the normal
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-- flow with a modified version of the INT instruction
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-- flow with a modified version of the INT instruction
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if( BRK_Implements_WAI )then
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if( BRK_Implements_WAI )then
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CPU_Next_State <= WAIT_FOR_INT;
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CPU_Next_State <= WAIT_FOR_INT;
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PC_Ctrl.Oper <= PC_INCR;
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PC_Ctrl.Offset <= PC_NEXT;
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end if;
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end if;
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when SOP_JMP =>
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when SOP_JMP =>
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CPU_Next_State <= JMP_C1;
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CPU_Next_State <= JMP_C1;
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Cache_Ctrl <= CACHE_OPER1;
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Cache_Ctrl <= CACHE_OPER1;
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when SOP_SMSK =>
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when SOP_SMSK =>
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PC_Ctrl.Oper <= PC_INCR;
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PC_Ctrl.Offset <= PC_NEXT;
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INT_Ctrl.Mask_Set <= '1';
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INT_Ctrl.Mask_Set <= '1';
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when SOP_GMSK =>
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when SOP_GMSK =>
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PC_Ctrl.Oper <= PC_INCR;
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PC_Ctrl.Offset <= PC_NEXT;
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ALU_Ctrl.Oper<= ALU_LDI;
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ALU_Ctrl.Oper <= ALU_GMSK;
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ALU_Ctrl.Reg <= ACCUM;
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ALU_Ctrl.Data<= Int_Mask;
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when SOP_JSR =>
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when SOP_JSR =>
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CPU_Next_State <= JSR_C1;
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CPU_Next_State <= JSR_C1;
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Cache_Ctrl <= CACHE_OPER1;
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Cache_Ctrl <= CACHE_OPER1;
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DP_Ctrl.Src <= DATA_WR_PC;
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DP_Ctrl.Src <= DATA_WR_PC;
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Line 446... |
-- to the ALU writing the result to registers. As a result, this
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-- to the ALU writing the result to registers. As a result, this
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-- state needs to idle the ALU initially, and back the PC up by 1
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-- state needs to idle the ALU initially, and back the PC up by 1
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-- We can get away with only 1 extra clock by pre-fetching the
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-- We can get away with only 1 extra clock by pre-fetching the
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-- next instruction, though.
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-- next instruction, though.
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Cache_Ctrl <= CACHE_PREFETCH;
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Cache_Ctrl <= CACHE_PREFETCH;
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PC_Ctrl.Oper <= PC_REV1;
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PC_Ctrl.Offset <= PC_REV1;
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-- Note that both the multiply process AND ALU process need the
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-- Note that both the multiply process AND ALU process need the
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-- source register for Rn (R1:R0 = R0 * Rn). Assert ALU_Ctrl.reg
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-- source register for Rn (R1:R0 = R0 * Rn). Assert ALU_Ctrl.reg
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-- now, but hold off on the ALU command until the next state.
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-- now, but hold off on the ALU command until the next state.
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ALU_Ctrl.Oper <= ALU_IDLE;
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ALU_Ctrl.Oper <= ALU_IDLE;
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ALU_Ctrl.Reg <= SubOp;
|
ALU_Ctrl.Reg <= SubOp;
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|
|
when OP_UPP =>
|
when OP_UPP =>
|
CPU_Next_State <= UPP_C1;
|
CPU_Next_State <= UPP_C1;
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Cache_Ctrl <= CACHE_PREFETCH;
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Cache_Ctrl <= CACHE_PREFETCH;
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PC_Ctrl.Oper <= PC_REV1;
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PC_Ctrl.Offset <= PC_REV1;
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ALU_Ctrl.Oper <= Opcode;
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ALU_Ctrl.Oper <= Opcode;
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ALU_Ctrl.Reg <= SubOp;
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ALU_Ctrl.Reg <= SubOp;
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|
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when OP_LDA =>
|
when OP_LDA =>
|
CPU_Next_State <= LDA_C1;
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CPU_Next_State <= LDA_C1;
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Cache_Ctrl <= CACHE_OPER1;
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Cache_Ctrl <= CACHE_OPER1;
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|
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when OP_LDI =>
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when OP_LDI =>
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CPU_Next_State <= LDI_C1;
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CPU_Next_State <= LDI_C1;
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Cache_Ctrl <= CACHE_OPER1;
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Cache_Ctrl <= CACHE_OPER1;
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PC_Ctrl.Oper <= PC_INCR;
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PC_Ctrl.Offset <= PC_NEXT;
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|
|
|
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when OP_LDO =>
|
when OP_LDO =>
|
CPU_Next_State <= LDO_C1;
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CPU_Next_State <= LDO_C1;
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Cache_Ctrl <= CACHE_OPER1;
|
Cache_Ctrl <= CACHE_OPER1;
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PC_Ctrl.Oper <= PC_REV2;
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PC_Ctrl.Offset <= PC_REV2;
|
|
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when OP_LDX =>
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when OP_LDX =>
|
CPU_Next_State <= LDX_C1;
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CPU_Next_State <= LDX_C1;
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Cache_Ctrl <= CACHE_PREFETCH;
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Cache_Ctrl <= CACHE_PREFETCH;
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PC_Ctrl.Oper <= PC_REV2;
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PC_Ctrl.Offset <= PC_REV2;
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|
|
when OP_STA =>
|
when OP_STA =>
|
CPU_Next_State <= STA_C1;
|
CPU_Next_State <= STA_C1;
|
Cache_Ctrl <= CACHE_OPER1;
|
Cache_Ctrl <= CACHE_OPER1;
|
|
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when OP_STO =>
|
when OP_STO =>
|
CPU_Next_State <= STO_C1;
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CPU_Next_State <= STO_C1;
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Cache_Ctrl <= CACHE_OPER1;
|
Cache_Ctrl <= CACHE_OPER1;
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PC_Ctrl.Oper <= PC_REV2;
|
PC_Ctrl.Offset <= PC_REV2;
|
DP_Ctrl.Src <= DATA_WR_REG;
|
DP_Ctrl.Src <= DATA_WR_REG;
|
DP_Ctrl.Reg <= ACCUM;
|
DP_Ctrl.Reg <= ACCUM;
|
|
|
when OP_STX =>
|
when OP_STX =>
|
CPU_Next_State <= STX_C1;
|
CPU_Next_State <= STX_C1;
|
Cache_Ctrl <= CACHE_PREFETCH;
|
Cache_Ctrl <= CACHE_PREFETCH;
|
PC_Ctrl.Oper <= PC_REV2;
|
PC_Ctrl.Offset <= PC_REV2;
|
DP_Ctrl.Src <= DATA_WR_REG;
|
DP_Ctrl.Src <= DATA_WR_REG;
|
DP_Ctrl.Reg <= ACCUM;
|
DP_Ctrl.Reg <= ACCUM;
|
|
|
when others =>
|
when others =>
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
ALU_Ctrl.Oper <= Opcode;
|
ALU_Ctrl.Oper <= Opcode;
|
ALU_Ctrl.Reg <= SubOp;
|
ALU_Ctrl.Reg <= SubOp;
|
|
|
end case;
|
end case;
|
|
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| Line 507... |
Line 512... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
when BRN_C1 =>
|
when BRN_C1 =>
|
CPU_Next_State <= INSTR_DECODE;
|
CPU_Next_State <= INSTR_DECODE;
|
Cache_Ctrl <= CACHE_INSTR;
|
Cache_Ctrl <= CACHE_INSTR;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
if( Flags(Reg) = Opcode(0) )then
|
if( Flags(Reg) = Opcode(0) )then
|
CPU_Next_State <= PIPE_FILL_0;
|
CPU_Next_State <= PIPE_FILL_0;
|
Cache_Ctrl <= CACHE_IDLE;
|
Cache_Ctrl <= CACHE_IDLE;
|
PC_Ctrl.Offset <= Operand1;
|
PC_Ctrl.Offset <= Operand1;
|
end if;
|
end if;
|
|
|
when DBNZ_C1 =>
|
when DBNZ_C1 =>
|
CPU_Next_State <= INSTR_DECODE;
|
CPU_Next_State <= INSTR_DECODE;
|
Cache_Ctrl <= CACHE_INSTR;
|
Cache_Ctrl <= CACHE_INSTR;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
if( Flags(FL_ZERO) = '0' )then
|
if( Flags(PSR_Z) = '0' )then
|
CPU_Next_State <= PIPE_FILL_0;
|
CPU_Next_State <= PIPE_FILL_0;
|
Cache_Ctrl <= CACHE_IDLE;
|
Cache_Ctrl <= CACHE_IDLE;
|
PC_Ctrl.Offset <= Operand1;
|
PC_Ctrl.Offset <= Operand1;
|
end if;
|
end if;
|
|
|
| Line 531... |
Line 536... |
Cache_Ctrl <= CACHE_OPER2;
|
Cache_Ctrl <= CACHE_OPER2;
|
|
|
when JMP_C2 =>
|
when JMP_C2 =>
|
CPU_Next_State <= PIPE_FILL_0;
|
CPU_Next_State <= PIPE_FILL_0;
|
PC_Ctrl.Oper <= PC_LOAD;
|
PC_Ctrl.Oper <= PC_LOAD;
|
PC_Ctrl.Addr <= Operand2 & Operand1;
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Data Storage - Load from memory (LDA, LDI, LDO, LDX)
|
-- Data Storage - Load from memory (LDA, LDI, LDO, LDX)
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
| Line 546... |
Line 550... |
when LDA_C2 =>
|
when LDA_C2 =>
|
CPU_Next_State <= LDA_C3;
|
CPU_Next_State <= LDA_C3;
|
|
|
when LDA_C3 =>
|
when LDA_C3 =>
|
CPU_Next_State <= LDA_C4;
|
CPU_Next_State <= LDA_C4;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
|
|
when LDA_C4 =>
|
when LDA_C4 =>
|
CPU_Next_State <= LDI_C1;
|
CPU_Next_State <= LDI_C1;
|
Cache_Ctrl <= CACHE_OPER1;
|
Cache_Ctrl <= CACHE_OPER1;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
|
|
when LDI_C1 =>
|
when LDI_C1 =>
|
CPU_Next_State <= INSTR_DECODE;
|
CPU_Next_State <= INSTR_DECODE;
|
Cache_Ctrl <= CACHE_INSTR;
|
Cache_Ctrl <= CACHE_INSTR;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
ALU_Ctrl.Oper <= ALU_LDI;
|
ALU_Ctrl.Oper <= ALU_LDI;
|
ALU_Ctrl.Reg <= SubOp;
|
ALU_Ctrl.Reg <= SubOp;
|
ALU_Ctrl.Data <= Operand1;
|
|
|
|
when LDO_C1 =>
|
when LDO_C1 =>
|
CPU_Next_State <= LDX_C2;
|
CPU_Next_State <= LDX_C2;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
if( Enable_Auto_Increment and SubOp(0) = '1' )then
|
if( Enable_Auto_Increment and SubOp(0) = '1' )then
|
ALU_Ctrl.Oper <= ALU_UPP;
|
ALU_Ctrl.Oper <= ALU_UPP;
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
end if;
|
end if;
|
|
|
| Line 578... |
Line 581... |
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
end if;
|
end if;
|
|
|
when LDX_C2 =>
|
when LDX_C2 =>
|
CPU_Next_State <= LDX_C3;
|
CPU_Next_State <= LDX_C3;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
|
|
when LDX_C3 =>
|
when LDX_C3 =>
|
CPU_Next_State <= LDX_C4;
|
CPU_Next_State <= LDX_C4;
|
Cache_Ctrl <= CACHE_OPER1;
|
Cache_Ctrl <= CACHE_OPER1;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
|
|
when LDX_C4 =>
|
when LDX_C4 =>
|
CPU_Next_State <= INSTR_DECODE;
|
CPU_Next_State <= INSTR_DECODE;
|
Cache_Ctrl <= CACHE_INSTR;
|
Cache_Ctrl <= CACHE_INSTR;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
ALU_Ctrl.Oper <= ALU_LDI;
|
ALU_Ctrl.Oper <= ALU_LDI;
|
ALU_Ctrl.Reg <= ACCUM;
|
ALU_Ctrl.Reg <= ACCUM;
|
ALU_Ctrl.Data <= Operand1;
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Data Storage - Store to memory (STA, STO, STX)
|
-- Data Storage - Store to memory (STA, STO, STX)
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
when STA_C1 =>
|
when STA_C1 =>
|
| Line 604... |
Line 606... |
DP_Ctrl.Src <= DATA_WR_REG;
|
DP_Ctrl.Src <= DATA_WR_REG;
|
DP_Ctrl.Reg <= SubOp;
|
DP_Ctrl.Reg <= SubOp;
|
|
|
when STA_C2 =>
|
when STA_C2 =>
|
CPU_Next_State <= STA_C3;
|
CPU_Next_State <= STA_C3;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
|
|
when STA_C3 =>
|
when STA_C3 =>
|
CPU_Next_State <= PIPE_FILL_2;
|
CPU_Next_State <= PIPE_FILL_2;
|
Cache_Ctrl <= CACHE_PREFETCH;
|
Cache_Ctrl <= CACHE_PREFETCH;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
|
|
when STO_C1 =>
|
when STO_C1 =>
|
CPU_Next_State <= PIPE_FILL_0;
|
CPU_Next_State <= PIPE_FILL_0;
|
Cache_Ctrl <= CACHE_PREFETCH;
|
Cache_Ctrl <= CACHE_PREFETCH;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
if( Enable_Auto_Increment and SubOp(0) = '1' )then
|
if( Enable_Auto_Increment and SubOp(0) = '1' )then
|
CPU_Next_State <= STO_C2;
|
CPU_Next_State <= STO_C2;
|
ALU_Ctrl.Oper <= ALU_UPP;
|
ALU_Ctrl.Oper <= ALU_UPP;
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
end if;
|
end if;
|
|
|
when STO_C2 =>
|
when STO_C2 =>
|
CPU_Next_State <= PIPE_FILL_1;
|
CPU_Next_State <= PIPE_FILL_1;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
ALU_Ctrl.Oper <= ALU_UPP2;
|
ALU_Ctrl.Oper <= ALU_UPP2;
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '1';
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '1';
|
|
|
when STX_C1 =>
|
when STX_C1 =>
|
CPU_Next_State <= PIPE_FILL_1;
|
CPU_Next_State <= PIPE_FILL_1;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
if( Enable_Auto_Increment and SubOp(0) = '1' )then
|
if( Enable_Auto_Increment and SubOp(0) = '1' )then
|
CPU_Next_State <= STX_C2;
|
CPU_Next_State <= STX_C2;
|
ALU_Ctrl.Oper <= ALU_UPP;
|
ALU_Ctrl.Oper <= ALU_UPP;
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '0';
|
end if;
|
end if;
|
|
|
when STX_C2 =>
|
when STX_C2 =>
|
CPU_Next_State <= PIPE_FILL_2;
|
CPU_Next_State <= PIPE_FILL_2;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
ALU_Ctrl.Oper <= ALU_UPP2;
|
ALU_Ctrl.Oper <= ALU_UPP2;
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '1';
|
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '1';
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Multi-Cycle Math Operations (UPP, MUL)
|
-- Multi-Cycle Math Operations (UPP, MUL)
|
| Line 652... |
Line 654... |
-- instruction/first operand, we have to return through PF2. Also, we
|
-- instruction/first operand, we have to return through PF2. Also, we
|
-- need to tell the ALU to store the results to R1:R0 here. Note that
|
-- need to tell the ALU to store the results to R1:R0 here. Note that
|
-- there is no ALU_Ctrl.Reg, as this is implied in the ALU instruction
|
-- there is no ALU_Ctrl.Reg, as this is implied in the ALU instruction
|
when MUL_C1 =>
|
when MUL_C1 =>
|
CPU_Next_State <= PIPE_FILL_2;
|
CPU_Next_State <= PIPE_FILL_2;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
ALU_Ctrl.Oper <= ALU_MUL;
|
ALU_Ctrl.Oper <= ALU_MUL;
|
|
|
when UPP_C1 =>
|
when UPP_C1 =>
|
CPU_Next_State <= PIPE_FILL_2;
|
CPU_Next_State <= PIPE_FILL_2;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
ALU_Ctrl.Oper <= ALU_UPP2;
|
ALU_Ctrl.Oper <= ALU_UPP2;
|
ALU_Ctrl.Reg <= SubOp_p1;
|
ALU_Ctrl.Reg <= SubOp_p1;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Basic Stack Manipulation (PSH, POP, RSP)
|
-- Basic Stack Manipulation (PSH, POP, RSP)
|
| Line 673... |
Line 675... |
when POP_C1 =>
|
when POP_C1 =>
|
CPU_Next_State <= POP_C2;
|
CPU_Next_State <= POP_C2;
|
|
|
when POP_C2 =>
|
when POP_C2 =>
|
CPU_Next_State <= POP_C3;
|
CPU_Next_State <= POP_C3;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
|
|
when POP_C3 =>
|
when POP_C3 =>
|
CPU_Next_State <= POP_C4;
|
CPU_Next_State <= POP_C4;
|
Cache_Ctrl <= CACHE_OPER1;
|
Cache_Ctrl <= CACHE_OPER1;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
|
|
when POP_C4 =>
|
when POP_C4 =>
|
CPU_Next_State <= INSTR_DECODE;
|
CPU_Next_State <= INSTR_DECODE;
|
Cache_Ctrl <= CACHE_INSTR;
|
Cache_Ctrl <= CACHE_INSTR;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
ALU_Ctrl.Oper <= ALU_POP;
|
ALU_Ctrl.Oper <= ALU_POP;
|
ALU_Ctrl.Reg <= SubOp;
|
ALU_Ctrl.Reg <= SubOp;
|
ALU_Ctrl.Data <= Operand1;
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Subroutines & Interrupts (RTS, JSR)
|
-- Subroutines & Interrupts (RTS, JSR)
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
when WAIT_FOR_INT => -- For soft interrupts only, halt the Program_Ctr
|
when WAIT_FOR_INT => -- For soft interrupts only, halt the Program_Ctr
|
| Line 707... |
Line 708... |
|
|
when ISR_C3 =>
|
when ISR_C3 =>
|
CPU_Next_State <= JSR_C1;
|
CPU_Next_State <= JSR_C1;
|
Cache_Ctrl <= CACHE_OPER1;
|
Cache_Ctrl <= CACHE_OPER1;
|
ALU_Ctrl.Oper <= ALU_STP;
|
ALU_Ctrl.Oper <= ALU_STP;
|
ALU_Ctrl.Reg <= INT_FLAG;
|
ALU_Ctrl.Reg <= conv_std_logic_vector(PSR_I,3);
|
SP_Ctrl.Oper <= SP_PUSH;
|
SP_Ctrl.Oper <= SP_PUSH;
|
DP_Ctrl.Src <= DATA_WR_PC;
|
DP_Ctrl.Src <= DATA_WR_PC;
|
DP_Ctrl.Reg <= PC_MSB;
|
DP_Ctrl.Reg <= PC_MSB;
|
Ack_D <= '1';
|
Ack_D <= '1';
|
|
|
| Line 723... |
Line 724... |
DP_Ctrl.Reg <= PC_LSB;
|
DP_Ctrl.Reg <= PC_LSB;
|
|
|
when JSR_C2 =>
|
when JSR_C2 =>
|
CPU_Next_State <= PIPE_FILL_0;
|
CPU_Next_State <= PIPE_FILL_0;
|
PC_Ctrl.Oper <= PC_LOAD;
|
PC_Ctrl.Oper <= PC_LOAD;
|
PC_Ctrl.Addr <= Operand2 & Operand1;
|
|
SP_Ctrl.Oper <= SP_PUSH;
|
SP_Ctrl.Oper <= SP_PUSH;
|
|
|
when RTS_C1 =>
|
when RTS_C1 =>
|
CPU_Next_State <= RTS_C2;
|
CPU_Next_State <= RTS_C2;
|
SP_Ctrl.Oper <= SP_POP;
|
SP_Ctrl.Oper <= SP_POP;
|
| Line 748... |
Line 748... |
Cache_Ctrl <= CACHE_OPER2;
|
Cache_Ctrl <= CACHE_OPER2;
|
|
|
when RTS_C5 =>
|
when RTS_C5 =>
|
CPU_Next_State <= PIPE_FILL_0;
|
CPU_Next_State <= PIPE_FILL_0;
|
PC_Ctrl.Oper <= PC_LOAD;
|
PC_Ctrl.Oper <= PC_LOAD;
|
PC_Ctrl.Addr <= Operand2 & Operand1;
|
-- if this is an RTI, then we need to clear the I bit
|
if( SubOp = SOP_RTI )then
|
if( SubOp = SOP_RTI )then
|
CPU_Next_State <= RTI_C6;
|
CPU_Next_State <= RTI_C6;
|
Cache_Ctrl <= CACHE_OPER1;
|
Cache_Ctrl <= CACHE_OPER1;
|
|
ALU_Ctrl.Oper <= ALU_CLP;
|
|
ALU_Ctrl.Reg <= conv_std_logic_vector(PSR_I,3);
|
end if;
|
end if;
|
|
|
when RTI_C6 =>
|
when RTI_C6 =>
|
CPU_Next_State <= PIPE_FILL_1;
|
CPU_Next_State <= PIPE_FILL_1;
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_NEXT;
|
ALU_Ctrl.Oper <= ALU_RFLG;
|
ALU_Ctrl.Oper <= ALU_RFLG;
|
ALU_Ctrl.Data <= Operand1;
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Debugging (BRK) Performs a 5-clock NOP
|
-- Debugging (BRK) Performs a 5-clock NOP
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
when BRK_C1 =>
|
when BRK_C1 =>
|
| Line 777... |
Line 778... |
if( Int_Req = '1' )then
|
if( Int_Req = '1' )then
|
if( CPU_State = INSTR_DECODE or CPU_State = WAIT_FOR_INT )then
|
if( CPU_State = INSTR_DECODE or CPU_State = WAIT_FOR_INT )then
|
CPU_Next_State <= ISR_C1;
|
CPU_Next_State <= ISR_C1;
|
Cache_Ctrl <= CACHE_IDLE;
|
Cache_Ctrl <= CACHE_IDLE;
|
-- Rewind the PC by 3 to compensate for the pipeline registers
|
-- Rewind the PC by 3 to compensate for the pipeline registers
|
PC_Ctrl.Oper <= PC_INCR;
|
PC_Ctrl.Offset <= PC_REV3;
|
PC_Ctrl.Offset <= x"FF";
|
|
-- Reset all of the sub-block controls to IDLE, to avoid unintended
|
-- Reset all of the sub-block controls to IDLE, to avoid unintended
|
-- operation due to the current instruction
|
-- operation due to the current instruction
|
ALU_Ctrl.Oper <= ALU_IDLE;
|
ALU_Ctrl.Oper <= ALU_IDLE;
|
SP_Ctrl.Oper <= SP_IDLE;
|
SP_Ctrl.Oper <= SP_IDLE;
|
DP_Ctrl.Src <= DATA_RD_MEM;
|
DP_Ctrl.Src <= DATA_RD_MEM;
|
| Line 880... |
Line 880... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
Offset_SX(15 downto 8) := (others => PC_Ctrl.Offset(7));
|
Offset_SX(15 downto 8) := (others => PC_Ctrl.Offset(7));
|
Offset_SX(7 downto 0) := PC_Ctrl.Offset;
|
Offset_SX(7 downto 0) := PC_Ctrl.Offset;
|
|
|
case PC_Ctrl.Oper is
|
case PC_Ctrl.Oper is
|
when PC_IDLE =>
|
|
null;
|
|
|
|
when PC_REV1 =>
|
|
Program_Ctr <= Program_Ctr - 1;
|
|
|
|
when PC_REV2 =>
|
|
Program_Ctr <= Program_Ctr - 2;
|
|
|
|
when PC_INCR =>
|
when PC_INCR =>
|
Program_Ctr <= Program_Ctr + Offset_SX - 2;
|
Program_Ctr <= Program_Ctr + Offset_SX - 2;
|
|
|
when PC_LOAD =>
|
when PC_LOAD =>
|
Program_Ctr <= PC_Ctrl.Addr;
|
Program_Ctr <= Operand2 & Operand1;
|
|
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
|
|
| Line 975... |
Line 966... |
|
|
if( Wait_for_FSM = '0' )then
|
if( Wait_for_FSM = '0' )then
|
if( Pending(0) = '1' )then
|
if( Pending(0) = '1' )then
|
ISR_Addr <= INT_VECTOR_0;
|
ISR_Addr <= INT_VECTOR_0;
|
Pending(0) <= '0';
|
Pending(0) <= '0';
|
Wait_for_FSM <= '1';
|
|
elsif( Pending(1) = '1' )then
|
elsif( Pending(1) = '1' )then
|
ISR_Addr <= INT_VECTOR_1;
|
ISR_Addr <= INT_VECTOR_1;
|
Pending(1) <= '0';
|
Pending(1) <= '0';
|
Wait_for_FSM <= '1';
|
|
elsif( Pending(2) = '1' )then
|
elsif( Pending(2) = '1' )then
|
ISR_Addr <= INT_VECTOR_2;
|
ISR_Addr <= INT_VECTOR_2;
|
Pending(2) <= '0';
|
Pending(2) <= '0';
|
Wait_for_FSM <= '1';
|
|
elsif( Pending(3) = '1' )then
|
elsif( Pending(3) = '1' )then
|
ISR_Addr <= INT_VECTOR_3;
|
ISR_Addr <= INT_VECTOR_3;
|
Pending(3) <= '0';
|
Pending(3) <= '0';
|
Wait_for_FSM <= '1';
|
|
elsif( Pending(4) = '1' )then
|
elsif( Pending(4) = '1' )then
|
ISR_Addr <= INT_VECTOR_4;
|
ISR_Addr <= INT_VECTOR_4;
|
Pending(4) <= '0';
|
Pending(4) <= '0';
|
Wait_for_FSM <= '1';
|
|
elsif( Pending(5) = '1' )then
|
elsif( Pending(5) = '1' )then
|
ISR_Addr <= INT_VECTOR_5;
|
ISR_Addr <= INT_VECTOR_5;
|
Pending(5) <= '0';
|
Pending(5) <= '0';
|
Wait_for_FSM <= '1';
|
|
elsif( Pending(6) = '1' )then
|
elsif( Pending(6) = '1' )then
|
ISR_Addr <= INT_VECTOR_6;
|
ISR_Addr <= INT_VECTOR_6;
|
Pending(6) <= '0';
|
Pending(6) <= '0';
|
Wait_for_FSM <= '1';
|
|
elsif( Pending(7) = '1' )then
|
elsif( Pending(7) = '1' )then
|
ISR_Addr <= INT_VECTOR_7;
|
ISR_Addr <= INT_VECTOR_7;
|
Pending(7) <= '0';
|
Pending(7) <= '0';
|
Wait_for_FSM <= '1';
|
|
end if;
|
end if;
|
|
Wait_for_FSM <= or_reduce(Pending);
|
end if;
|
end if;
|
|
|
-- Reset the Wait_for_FSM flag on Int_Ack
|
-- Reset the Wait_for_FSM flag on Int_Ack
|
Ack_Q <= Ack_D;
|
Ack_Q <= Ack_D;
|
Ack_Q1 <= Ack_Q;
|
Ack_Q1 <= Ack_Q;
|
| Line 1034... |
Line 1018... |
|
|
case ALU_Ctrl.Oper is
|
case ALU_Ctrl.Oper is
|
when ALU_INC => -- Rn = Rn + 1 : Flags N,C,Z
|
when ALU_INC => -- Rn = Rn + 1 : Flags N,C,Z
|
Sum := ("0" & x"01") +
|
Sum := ("0" & x"01") +
|
("0" & Regfile(Index));
|
("0" & Regfile(Index));
|
Flags(FL_ZERO) <= nor_reduce(Sum(7 downto 0));
|
Flags(PSR_Z) <= nor_reduce(Sum(7 downto 0));
|
Flags(FL_CARRY) <= Sum(8);
|
Flags(PSR_C) <= Sum(8);
|
Flags(FL_NEG) <= Sum(7);
|
Flags(PSR_N) <= Sum(7);
|
Regfile(Index) <= Sum(7 downto 0);
|
Regfile(Index) <= Sum(7 downto 0);
|
|
|
when ALU_UPP => -- Rn = Rn + 1
|
when ALU_UPP => -- Rn = Rn + 1
|
Sum := ("0" & x"01") +
|
Sum := ("0" & x"01") +
|
("0" & Regfile(Index));
|
("0" & Regfile(Index));
|
Flags(FL_CARRY) <= Sum(8);
|
Flags(PSR_C) <= Sum(8);
|
Regfile(Index) <= Sum(7 downto 0);
|
Regfile(Index) <= Sum(7 downto 0);
|
|
|
when ALU_UPP2 => -- Rn = Rn + C
|
when ALU_UPP2 => -- Rn = Rn + C
|
Sum := ("0" & x"00") +
|
Sum := ("0" & x"00") +
|
("0" & Regfile(Index)) +
|
("0" & Regfile(Index)) +
|
Flags(FL_CARRY);
|
Flags(PSR_C);
|
Flags(FL_CARRY) <= Sum(8);
|
Flags(PSR_C) <= Sum(8);
|
Regfile(Index) <= Sum(7 downto 0);
|
Regfile(Index) <= Sum(7 downto 0);
|
|
|
when ALU_ADC => -- R0 = R0 + Rn + C : Flags N,C,Z
|
when ALU_ADC => -- R0 = R0 + Rn + C : Flags N,C,Z
|
Sum := ("0" & Regfile(0)) +
|
Sum := ("0" & Regfile(0)) +
|
("0" & Regfile(Index)) +
|
("0" & Regfile(Index)) +
|
Flags(FL_CARRY);
|
Flags(PSR_C);
|
Flags(FL_ZERO) <= nor_reduce(Sum(7 downto 0));
|
Flags(PSR_Z) <= nor_reduce(Sum(7 downto 0));
|
Flags(FL_CARRY) <= Sum(8);
|
Flags(PSR_C) <= Sum(8);
|
Flags(FL_NEG) <= Sum(7);
|
Flags(PSR_N) <= Sum(7);
|
Regfile(0) <= Sum(7 downto 0);
|
Regfile(0) <= Sum(7 downto 0);
|
|
|
when ALU_TX0 => -- R0 = Rn : Flags N,Z
|
when ALU_TX0 => -- R0 = Rn : Flags N,Z
|
Temp := "0" & Regfile(Index);
|
Temp := "0" & Regfile(Index);
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
Flags(PSR_Z) <= nor_reduce(Temp(7 downto 0));
|
Flags(FL_NEG) <= Temp(7);
|
Flags(PSR_N) <= Temp(7);
|
Regfile(0) <= Temp(7 downto 0);
|
Regfile(0) <= Temp(7 downto 0);
|
|
|
when ALU_OR => -- R0 = R0 | Rn : Flags N,Z
|
when ALU_OR => -- R0 = R0 | Rn : Flags N,Z
|
Temp(7 downto 0) := Regfile(0) or Regfile(Index);
|
Temp(7 downto 0) := Regfile(0) or Regfile(Index);
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
Flags(PSR_Z) <= nor_reduce(Temp(7 downto 0));
|
Flags(FL_NEG) <= Temp(7);
|
Flags(PSR_N) <= Temp(7);
|
Regfile(0) <= Temp(7 downto 0);
|
Regfile(0) <= Temp(7 downto 0);
|
|
|
when ALU_AND => -- R0 = R0 & Rn : Flags N,Z
|
when ALU_AND => -- R0 = R0 & Rn : Flags N,Z
|
Temp(7 downto 0) := Regfile(0) and Regfile(Index);
|
Temp(7 downto 0) := Regfile(0) and Regfile(Index);
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
Flags(PSR_Z) <= nor_reduce(Temp(7 downto 0));
|
Flags(FL_NEG) <= Temp(7);
|
Flags(PSR_N) <= Temp(7);
|
Regfile(0) <= Temp(7 downto 0);
|
Regfile(0) <= Temp(7 downto 0);
|
|
|
when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z
|
when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z
|
Temp(7 downto 0) := Regfile(0) xor Regfile(Index);
|
Temp(7 downto 0) := Regfile(0) xor Regfile(Index);
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
Flags(PSR_Z) <= nor_reduce(Temp(7 downto 0));
|
Flags(FL_NEG) <= Temp(7);
|
Flags(PSR_N) <= Temp(7);
|
Regfile(0) <= Temp(7 downto 0);
|
Regfile(0) <= Temp(7 downto 0);
|
|
|
when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z
|
when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z
|
Temp := Regfile(Index) & Flags(FL_CARRY);
|
Temp := Regfile(Index) & Flags(PSR_C);
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
Flags(PSR_Z) <= nor_reduce(Temp(7 downto 0));
|
Flags(FL_CARRY) <= Temp(8);
|
Flags(PSR_C) <= Temp(8);
|
Flags(FL_NEG) <= Temp(7);
|
Flags(PSR_N) <= Temp(7);
|
Regfile(Index) <= Temp(7 downto 0);
|
Regfile(Index) <= Temp(7 downto 0);
|
|
|
when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z
|
when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z
|
Temp := Regfile(Index)(0) & Flags(FL_CARRY) &
|
Temp := Regfile(Index)(0) & Flags(PSR_C) &
|
Regfile(Index)(7 downto 1);
|
Regfile(Index)(7 downto 1);
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
Flags(PSR_Z) <= nor_reduce(Temp(7 downto 0));
|
Flags(FL_CARRY) <= Temp(8);
|
Flags(PSR_C) <= Temp(8);
|
Flags(FL_NEG) <= Temp(7);
|
Flags(PSR_N) <= Temp(7);
|
Regfile(Index) <= Temp(7 downto 0);
|
Regfile(Index) <= Temp(7 downto 0);
|
|
|
when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
|
when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
|
Sum := ("0" & Regfile(Index)) +
|
Sum := ("0" & Regfile(Index)) +
|
("0" & x"FF");
|
("0" & x"FF");
|
Flags(FL_ZERO) <= nor_reduce(Sum(7 downto 0));
|
Flags(PSR_Z) <= nor_reduce(Sum(7 downto 0));
|
Flags(FL_CARRY) <= Sum(8);
|
Flags(PSR_C) <= Sum(8);
|
Flags(FL_NEG) <= Sum(7);
|
Flags(PSR_N) <= Sum(7);
|
Regfile(Index) <= Sum(7 downto 0);
|
Regfile(Index) <= Sum(7 downto 0);
|
|
|
when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
|
when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
|
Sum := ("0" & Regfile(0)) +
|
Sum := ("0" & Regfile(0)) +
|
("1" & (not Regfile(Index))) +
|
("1" & (not Regfile(Index))) +
|
Flags(FL_CARRY);
|
Flags(PSR_C);
|
Flags(FL_ZERO) <= nor_reduce(Sum(7 downto 0));
|
Flags(PSR_Z) <= nor_reduce(Sum(7 downto 0));
|
Flags(FL_CARRY) <= Sum(8);
|
Flags(PSR_C) <= Sum(8);
|
Flags(FL_NEG) <= Sum(7);
|
Flags(PSR_N) <= Sum(7);
|
Regfile(0) <= Sum(7 downto 0);
|
Regfile(0) <= Sum(7 downto 0);
|
|
|
when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z
|
when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z
|
Sum := ("0" & Regfile(0)) +
|
Sum := ("0" & Regfile(0)) +
|
("0" & Regfile(Index));
|
("0" & Regfile(Index));
|
Flags(FL_CARRY) <= Sum(8);
|
Flags(PSR_C) <= Sum(8);
|
Regfile(0) <= Sum(7 downto 0);
|
Regfile(0) <= Sum(7 downto 0);
|
Flags(FL_ZERO) <= nor_reduce(Sum(7 downto 0));
|
Flags(PSR_Z) <= nor_reduce(Sum(7 downto 0));
|
Flags(FL_NEG) <= Sum(7);
|
Flags(PSR_N) <= Sum(7);
|
|
|
when ALU_STP => -- Sets bit(n) in the Flags register
|
when ALU_STP => -- Sets bit(n) in the Flags register
|
Flags(Index) <= '1';
|
Flags(Index) <= '1';
|
|
|
when ALU_BTT => -- Z = !R0(N), N = R0(7)
|
when ALU_BTT => -- Z = !R0(N), N = R0(7)
|
Flags(FL_ZERO) <= not Regfile(0)(Index);
|
Flags(PSR_Z) <= not Regfile(0)(Index);
|
Flags(FL_NEG) <= Regfile(0)(7);
|
Flags(PSR_N) <= Regfile(0)(7);
|
|
|
when ALU_CLP => -- Clears bit(n) in the Flags register
|
when ALU_CLP => -- Clears bit(n) in the Flags register
|
Flags(Index) <= '0';
|
Flags(Index) <= '0';
|
|
|
when ALU_T0X => -- Rn = R0 : Flags N,Z
|
when ALU_T0X => -- Rn = R0 : Flags N,Z
|
Temp := "0" & Regfile(0);
|
Temp := "0" & Regfile(0);
|
Flags(FL_ZERO) <= nor_reduce(Temp(7 downto 0));
|
Flags(PSR_Z) <= nor_reduce(Temp(7 downto 0));
|
Flags(FL_NEG) <= Temp(7);
|
Flags(PSR_N) <= Temp(7);
|
Regfile(Index) <= Temp(7 downto 0);
|
Regfile(Index) <= Temp(7 downto 0);
|
|
|
when ALU_CMP => -- Sets Flags on R0 - Rn : Flags N,C,Z
|
when ALU_CMP => -- Sets Flags on R0 - Rn : Flags N,C,Z
|
Sum := ("0" & Regfile(0)) +
|
Sum := ("0" & Regfile(0)) +
|
("1" & (not Regfile(Index))) +
|
("1" & (not Regfile(Index))) +
|
'1';
|
'1';
|
Flags(FL_ZERO) <= nor_reduce(Sum(7 downto 0));
|
Flags(PSR_Z) <= nor_reduce(Sum(7 downto 0));
|
Flags(FL_CARRY) <= Sum(8);
|
Flags(PSR_C) <= Sum(8);
|
Flags(FL_NEG) <= Sum(7);
|
Flags(PSR_N) <= Sum(7);
|
|
|
when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
|
when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
|
Regfile(0) <= Mult(7 downto 0);
|
Regfile(0) <= Mult(7 downto 0);
|
Regfile(1) <= Mult(15 downto 8);
|
Regfile(1) <= Mult(15 downto 8);
|
Flags(FL_ZERO) <= nor_reduce(Mult);
|
Flags(PSR_Z) <= nor_reduce(Mult);
|
|
|
when ALU_LDI => -- Rn <= Data : Flags N,Z
|
when ALU_LDI => -- Rn <= Data : Flags N,Z
|
Flags(FL_ZERO) <= nor_reduce(ALU_Ctrl.Data);
|
Flags(PSR_Z) <= nor_reduce(Operand1);
|
Flags(FL_NEG) <= ALU_Ctrl.Data(7);
|
Flags(PSR_N) <= Operand1(7);
|
Regfile(Index) <= ALU_Ctrl.Data;
|
Regfile(Index) <= Operand1;
|
|
|
when ALU_POP => -- Rn <= Data
|
when ALU_POP => -- Rn <= Data
|
Regfile(Index) <= ALU_Ctrl.Data;
|
Regfile(Index) <= Operand1;
|
|
|
when ALU_RFLG =>
|
when ALU_RFLG =>
|
Flags <= ALU_Ctrl.Data;
|
Flags <= Operand1;
|
|
|
when ALU_TSX =>
|
when ALU_RSP =>
|
Regfile(0) <= Stack_Ptr(7 downto 0);
|
Regfile(0) <= Stack_Ptr(7 downto 0);
|
Regfile(1) <= Stack_Ptr(15 downto 8);
|
Regfile(1) <= Stack_Ptr(15 downto 8);
|
|
|
|
when ALU_GMSK =>
|
|
Flags(PSR_Z) <= nor_reduce(Int_Mask);
|
|
Regfile(0) <= Int_Mask;
|
|
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
|
|
end if;
|
end if;
|
| Line 1187... |
Line 1175... |
|
|
Multiplier_proc: process( Clock )
|
Multiplier_proc: process( Clock )
|
begin
|
begin
|
if( rising_edge(Clock) )then
|
if( rising_edge(Clock) )then
|
Mult <= Regfile(0) *
|
Mult <= Regfile(0) *
|
Regfile(conv_integer(ALU_Ctrl.Reg));
|
|
end if;
|
|
end process;
|
|
|
|
end architecture;
|
|
|
|
No newline at end of file
|
No newline at end of file
|
