| Line 404... |
Line 404... |
ALU_Ctrl.Oper <= ALU_RSP;
|
ALU_Ctrl.Oper <= ALU_RSP;
|
end if;
|
end if;
|
|
|
when SOP_RTS | SOP_RTI =>
|
when SOP_RTS | SOP_RTI =>
|
CPU_Next_State <= RTS_C1;
|
CPU_Next_State <= RTS_C1;
|
Cache_Ctrl <= CACHE_IDLE;
|
|
SP_Ctrl.Oper <= SP_POP;
|
SP_Ctrl.Oper <= SP_POP;
|
|
|
when SOP_BRK =>
|
when SOP_BRK =>
|
CPU_Next_State <= BRK_C1;
|
CPU_Next_State <= BRK_C1;
|
PC_Ctrl.Offset <= PC_REV2;
|
PC_Ctrl.Offset <= PC_REV2;
|
| Line 505... |
Line 504... |
ALU_Ctrl.Oper <= Opcode;
|
ALU_Ctrl.Oper <= Opcode;
|
ALU_Ctrl.Reg <= SubOp;
|
ALU_Ctrl.Reg <= SubOp;
|
|
|
end case;
|
end case;
|
|
|
|
if( Int_Req = '1' )then
|
|
CPU_Next_State <= ISR_C1;
|
|
Cache_Ctrl <= CACHE_IDLE;
|
|
-- Rewind the PC by 3 to compensate for the pipeline registers
|
|
PC_Ctrl.Offset <= PC_REV3;
|
|
-- Reset all of the sub-block controls to IDLE, to avoid unintended
|
|
-- operation due to the current instruction
|
|
ALU_Ctrl.Oper <= ALU_IDLE;
|
|
SP_Ctrl.Oper <= SP_IDLE;
|
|
DP_Ctrl.Src <= DATA_RD_MEM;
|
|
INT_Ctrl.Soft_Ints <= (others => '0');
|
|
end if;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Program Control (BR0_C1, BR1_C1, DBNZ_C1, JMP )
|
-- Program Control (BR0_C1, BR1_C1, DBNZ_C1, JMP )
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
when BRN_C1 =>
|
when BRN_C1 =>
|
| Line 693... |
Line 705... |
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Subroutines & Interrupts (RTS, JSR)
|
-- Subroutines & Interrupts (RTS, JSR)
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
when WAIT_FOR_INT => -- For soft interrupts only, halt the Program_Ctr
|
when WAIT_FOR_INT => -- For soft interrupts only, halt the Program_Ctr
|
CPU_Next_State <= WAIT_FOR_INT;
|
|
DP_Ctrl.Src <= DATA_BUS_IDLE;
|
DP_Ctrl.Src <= DATA_BUS_IDLE;
|
|
if( Int_Req = '1' )then
|
|
CPU_Next_State <= ISR_C1;
|
|
-- Rewind the PC by 3 to compensate for the pipeline registers
|
|
PC_Ctrl.Offset <= PC_REV3;
|
|
-- Reset all of the sub-block controls to IDLE, to avoid unintended
|
|
-- operation due to the current instruction
|
|
DP_Ctrl.Src <= DATA_RD_MEM;
|
|
end if;
|
|
|
when ISR_C1 =>
|
when ISR_C1 =>
|
CPU_Next_State <= ISR_C2;
|
CPU_Next_State <= ISR_C2;
|
INT_Ctrl.Incr_ISR <= '1';
|
INT_Ctrl.Incr_ISR <= '1';
|
|
|
| Line 771... |
Line 790... |
|
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
|
|
-- Interrupt service routines can only begin during the decode and wait
|
|
-- states to avoid corruption due to incomplete instruction execution
|
|
if( Int_Req = '1' )then
|
|
if( CPU_State = INSTR_DECODE or CPU_State = WAIT_FOR_INT )then
|
|
CPU_Next_State <= ISR_C1;
|
|
Cache_Ctrl <= CACHE_IDLE;
|
|
-- Rewind the PC by 3 to compensate for the pipeline registers
|
|
PC_Ctrl.Offset <= PC_REV3;
|
|
-- Reset all of the sub-block controls to IDLE, to avoid unintended
|
|
-- operation due to the current instruction
|
|
ALU_Ctrl.Oper <= ALU_IDLE;
|
|
SP_Ctrl.Oper <= SP_IDLE;
|
|
DP_Ctrl.Src <= DATA_RD_MEM;
|
|
INT_Ctrl.Soft_Ints <= (others => '0');
|
|
|
|
end if;
|
|
end if;
|
|
|
|
end process;
|
end process;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Registered portion of CPU finite state machine
|
-- Registered portion of CPU finite state machine
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
| Line 1175... |
Line 1176... |
|
|
Multiplier_proc: process( Clock )
|
Multiplier_proc: process( Clock )
|
begin
|
begin
|
if( rising_edge(Clock) )then
|
if( rising_edge(Clock) )then
|
Mult <= Regfile(0) *
|
Mult <= Regfile(0) *
|
|
Regfile(conv_integer(ALU_Ctrl.Reg));
|
|
end if;
|
|
end process;
|
|
|
No newline at end of file
|
No newline at end of file
|
|
end architecture;
|
No newline at end of file
|
No newline at end of file
|
