URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_cpu.vhd] - Diff between revs 190 and 191
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 190 |
Rev 191 |
| Line 879... |
Line 879... |
Instr_Prefetch <= '0';
|
Instr_Prefetch <= '0';
|
Prefetch <= x"00";
|
Prefetch <= x"00";
|
|
|
CPU_Halt_Req <= '0';
|
CPU_Halt_Req <= '0';
|
|
|
Wr_Data <= x"00";
|
Wr_Data <= OPEN8_NULLBUS;
|
Wr_Enable <= '0';
|
Wr_Enable <= '0';
|
Rd_Enable <= '1';
|
Rd_Enable <= '1';
|
|
|
Program_Ctr <= Program_Start_Addr;
|
Program_Ctr <= Program_Start_Addr;
|
Stack_Ptr <= Stack_Start_Addr;
|
Stack_Ptr <= Stack_Start_Addr;
|
| Line 912... |
Line 912... |
elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
|
|
|
CPU_Halt_Req <= CPU_Halt;
|
CPU_Halt_Req <= CPU_Halt;
|
|
|
Wr_Enable <= '0';
|
Wr_Enable <= '0';
|
Wr_Data <= x"00";
|
Wr_Data <= OPEN8_NULLBUS;
|
Rd_Enable <= '0';
|
Rd_Enable <= '0';
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Instruction/Operand caching for pipelined memory access
|
-- Instruction/Operand caching for pipelined memory access
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.