| Line 192... |
Line 192... |
-- Seth Henry 03/17/20 Added generic to control whether RTI full restores
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-- Seth Henry 03/17/20 Added generic to control whether RTI full restores
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-- the flags, including the general purpose ones, or
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-- the flags, including the general purpose ones, or
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-- only the core ALU flags (Z, N, and C). Also
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-- only the core ALU flags (Z, N, and C). Also
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-- brought out copies of the GP flags for external
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-- brought out copies of the GP flags for external
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-- connection.
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-- connection.
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-- Seth Henry 04/09/20 Added a compile time setting to block interrupts
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-- while the I bit is set to avoid reentering ISRs
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-- This may slightly affect timing, as this will
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-- potentially block higher priority interrupts
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-- until the lower priority ISR returns or clears
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-- the I bit.
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-- Also added the I bit to the exported flags for
|
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-- use in memory protection schemes.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 212... |
Line 220... |
Allow_Stack_Address_Move : boolean := false; -- Use Normal v8 RSP
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Allow_Stack_Address_Move : boolean := false; -- Use Normal v8 RSP
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Stack_Xfer_Flag : integer := PSR_GP4; -- GP4 modifies RSP
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Stack_Xfer_Flag : integer := PSR_GP4; -- GP4 modifies RSP
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Enable_Auto_Increment : boolean := false; -- Modify indexed instr
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Enable_Auto_Increment : boolean := false; -- Modify indexed instr
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BRK_Implements_WAI : boolean := false; -- BRK -> Wait for Int
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BRK_Implements_WAI : boolean := false; -- BRK -> Wait for Int
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Enable_NMI : boolean := true; -- Force INTR0 enabled
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Enable_NMI : boolean := true; -- Force INTR0 enabled
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Sequential_Interrupts : boolean := false; -- Interruptable ISRs
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RTI_Ignores_GP_Flags : boolean := false; -- RTI restores all flags
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RTI_Ignores_GP_Flags : boolean := false; -- RTI restores all flags
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Default_Interrupt_Mask : DATA_TYPE := x"FF"; -- Enable all Ints
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Default_Interrupt_Mask : DATA_TYPE := x"FF"; -- Enable all Ints
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Reset_Level : std_logic := '0' ); -- Active reset level
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Reset_Level : std_logic := '0' ); -- Active reset level
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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| Line 276... |
Line 285... |
signal Int_Mask : DATA_TYPE := x"00";
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signal Int_Mask : DATA_TYPE := x"00";
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signal ISR_Addr : ADDRESS_TYPE := x"0000";
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signal ISR_Addr : ADDRESS_TYPE := x"0000";
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signal i_Ints : INTERRUPT_BUNDLE := x"00";
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signal i_Ints : INTERRUPT_BUNDLE := x"00";
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signal Pending : INTERRUPT_BUNDLE := x"00";
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signal Pending : INTERRUPT_BUNDLE := x"00";
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signal Wait_for_FSM : std_logic := '0';
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signal Wait_for_FSM : std_logic := '0';
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signal Wait_for_ISR : std_logic := '0';
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|
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begin
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begin
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|
|
|
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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| Line 893... |
Line 903... |
Int_Ack <= '0';
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Int_Ack <= '0';
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|
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Int_Req <= '0';
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Int_Req <= '0';
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Pending <= x"00";
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Pending <= x"00";
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Wait_for_FSM <= '0';
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Wait_for_FSM <= '0';
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Wait_for_ISR <= '0';
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if( Enable_NMI )then
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if( Enable_NMI )then
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Int_Mask <= Default_Interrupt_Mask(7 downto 1) & '1';
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Int_Mask <= Default_Interrupt_Mask(7 downto 1) & '1';
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else
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else
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Int_Mask <= Default_Interrupt_Mask;
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Int_Mask <= Default_Interrupt_Mask;
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end if;
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end if;
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| Line 905... |
Line 916... |
for i in 0 to 7 loop
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for i in 0 to 7 loop
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Regfile(i) <= x"00";
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Regfile(i) <= x"00";
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end loop;
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end loop;
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Flags <= x"00";
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Flags <= x"00";
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|
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GP_Flags <= x"0";
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GP_Flags <= (others => '0');
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|
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
|
|
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CPU_Halt_Req <= CPU_Halt;
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CPU_Halt_Req <= CPU_Halt;
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| Line 1034... |
Line 1045... |
i_Ints := (Interrupts or INT_Ctrl.Soft_Ints) and
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i_Ints := (Interrupts or INT_Ctrl.Soft_Ints) and
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Int_Mask;
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Int_Mask;
|
|
|
Pending <= i_Ints or Pending;
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Pending <= i_Ints or Pending;
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|
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if( Wait_for_FSM = '0' )then
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if( Sequential_Interrupts )then
|
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Wait_for_ISR <= Flags(PSR_I);
|
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else
|
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Wait_for_ISR <= '0';
|
|
end if;
|
|
|
|
if( Wait_for_FSM = '0' and Wait_for_ISR = '0' )then
|
if( Pending(0) = '1' )then
|
if( Pending(0) = '1' )then
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ISR_Addr <= INT_VECTOR_0;
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ISR_Addr <= INT_VECTOR_0;
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Pending(0) <= '0';
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Pending(0) <= '0';
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elsif( Pending(1) = '1' )then
|
elsif( Pending(1) = '1' )then
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ISR_Addr <= INT_VECTOR_1;
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ISR_Addr <= INT_VECTOR_1;
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| Line 1236... |
Line 1253... |
|
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when others =>
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when others =>
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null;
|
null;
|
end case;
|
end case;
|
|
|
GP_Flags <= Flags(7 downto 4);
|
GP_Flags <= Flags(7 downto 3);
|
|
|
end if;
|
end if;
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end process;
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end process;
|
|
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
|
