| Line 228... |
Line 228... |
Reset_Level : std_logic := '0' ); -- Active reset level
|
Reset_Level : std_logic := '0' ); -- Active reset level
|
port(
|
port(
|
Clock : in std_logic;
|
Clock : in std_logic;
|
Reset : in std_logic;
|
Reset : in std_logic;
|
CPU_Halt : in std_logic := '0';
|
CPU_Halt : in std_logic := '0';
|
Interrupts : in INTERRUPT_BUNDLE := x"00";
|
|
GP_Flags : out EXT_GP_FLAGS;
|
GP_Flags : out EXT_GP_FLAGS;
|
--
|
--
|
Address : out ADDRESS_TYPE;
|
Open8_Bus : out OPEN8_BUS_TYPE;
|
Rd_Data : in DATA_TYPE;
|
Rd_Data : in DATA_TYPE;
|
Rd_Enable : out std_logic;
|
Interrupts : in INTERRUPT_BUNDLE := x"00"
|
Wr_Data : out DATA_TYPE;
|
);
|
Wr_Enable : out std_logic );
|
|
end entity;
|
end entity;
|
|
|
architecture behave of o8_cpu is
|
architecture behave of o8_cpu is
|
|
|
constant INT_VECTOR_0 : ADDRESS_TYPE := ISR_Start_Addr;
|
constant INT_VECTOR_0 : ADDRESS_TYPE := ISR_Start_Addr;
|
| Line 314... |
Line 312... |
Offset_SX(7 downto 0) := Operand1;
|
Offset_SX(7 downto 0) := Operand1;
|
|
|
case( CPU_State )is
|
case( CPU_State )is
|
|
|
when LDA_C2 | STA_C2 =>
|
when LDA_C2 | STA_C2 =>
|
Address <= Operand2 & Operand1;
|
Open8_Bus.Address <= Operand2 & Operand1;
|
|
|
when LDX_C1 | STX_C1 =>
|
when LDX_C1 | STX_C1 =>
|
Address <= (Regfile(Reg_1) & Regfile(Reg));
|
Open8_Bus.Address <= (Regfile(Reg_1) & Regfile(Reg));
|
|
|
when LDO_C1 | STO_C1 =>
|
when LDO_C1 | STO_C1 =>
|
Address <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
|
Open8_Bus.Address <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
|
|
|
when ISR_C1 | ISR_C2 =>
|
when ISR_C1 | ISR_C2 =>
|
Address <= ISR_Addr;
|
Open8_Bus.Address <= ISR_Addr;
|
|
|
when PSH_C1 | POP_C1 | ISR_C3 | JSR_C1 | JSR_C2 | RTS_C1 | RTS_C2 | RTS_C3 =>
|
when PSH_C1 | POP_C1 | ISR_C3 | JSR_C1 | JSR_C2 | RTS_C1 | RTS_C2 | RTS_C3 =>
|
Address <= Stack_Ptr;
|
Open8_Bus.Address <= Stack_Ptr;
|
|
|
when others =>
|
when others =>
|
Address <= Program_Ctr;
|
Open8_Bus.Address <= Program_Ctr;
|
|
|
end case;
|
end case;
|
|
|
end process;
|
end process;
|
|
|
| Line 889... |
Line 887... |
Instr_Prefetch <= '0';
|
Instr_Prefetch <= '0';
|
Prefetch <= x"00";
|
Prefetch <= x"00";
|
|
|
CPU_Halt_Req <= '0';
|
CPU_Halt_Req <= '0';
|
|
|
Wr_Data <= OPEN8_NULLBUS;
|
Open8_Bus.Wr_En <= '0';
|
Wr_Enable <= '0';
|
Open8_Bus.Wr_Data <= OPEN8_NULLBUS;
|
Rd_Enable <= '1';
|
Open8_Bus.Rd_En <= '1';
|
|
|
Program_Ctr <= Program_Start_Addr;
|
Program_Ctr <= Program_Start_Addr;
|
Stack_Ptr <= Stack_Start_Addr;
|
Stack_Ptr <= Stack_Start_Addr;
|
|
|
Ack_Q <= '0';
|
Ack_Q <= '0';
|
| Line 922... |
Line 920... |
|
|
elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
|
|
|
CPU_Halt_Req <= CPU_Halt;
|
CPU_Halt_Req <= CPU_Halt;
|
|
|
Wr_Enable <= '0';
|
Open8_Bus.Wr_En <= '0';
|
Wr_Data <= OPEN8_NULLBUS;
|
Open8_Bus.Wr_Data <= OPEN8_NULLBUS;
|
Rd_Enable <= '0';
|
Open8_Bus.Rd_En <= '0';
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Instruction/Operand caching for pipelined memory access
|
-- Instruction/Operand caching for pipelined memory access
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
CPU_State <= CPU_Next_State;
|
CPU_State <= CPU_Next_State;
|
| Line 981... |
Line 979... |
case DP_Ctrl.Src is
|
case DP_Ctrl.Src is
|
when DATA_BUS_IDLE =>
|
when DATA_BUS_IDLE =>
|
null;
|
null;
|
|
|
when DATA_RD_MEM =>
|
when DATA_RD_MEM =>
|
Rd_Enable <= '1';
|
Open8_Bus.Rd_En <= '1';
|
|
|
when DATA_WR_REG =>
|
when DATA_WR_REG =>
|
Wr_Enable <= '1';
|
Open8_Bus.Wr_En <= '1';
|
Wr_Data <= Regfile(conv_integer(DP_Ctrl.Reg));
|
Open8_Bus.Wr_Data <= Regfile(conv_integer(DP_Ctrl.Reg));
|
|
|
when DATA_WR_FLAG =>
|
when DATA_WR_FLAG =>
|
Wr_Enable <= '1';
|
Open8_Bus.Wr_En <= '1';
|
Wr_Data <= Flags;
|
Open8_Bus.Wr_Data <= Flags;
|
|
|
when DATA_WR_PC =>
|
when DATA_WR_PC =>
|
Wr_Enable <= '1';
|
Open8_Bus.Wr_En <= '1';
|
Wr_Data <= Program_Ctr(15 downto 8);
|
Open8_Bus.Wr_Data <= Program_Ctr(15 downto 8);
|
if( DP_Ctrl.Reg = PC_LSB )then
|
if( DP_Ctrl.Reg = PC_LSB )then
|
Wr_Data <= Program_Ctr(7 downto 0);
|
Open8_Bus.Wr_Data <= Program_Ctr(7 downto 0);
|
end if;
|
end if;
|
|
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
