| Line 200... |
Line 200... |
-- potentially block higher priority interrupts
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-- potentially block higher priority interrupts
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-- until the lower priority ISR returns or clears
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-- until the lower priority ISR returns or clears
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-- the I bit.
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-- the I bit.
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-- Also added the I bit to the exported flags for
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-- Also added the I bit to the exported flags for
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-- use in memory protection schemes.
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-- use in memory protection schemes.
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-- Seth Henry 04/16/20 Modified to use new Open8 bus record. Also added
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-- reset and usec_tick logic to drive utility signals
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 221... |
Line 223... |
Stack_Xfer_Flag : integer := PSR_GP4; -- GP4 modifies RSP
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Stack_Xfer_Flag : integer := PSR_GP4; -- GP4 modifies RSP
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Enable_Auto_Increment : boolean := false; -- Modify indexed instr
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Enable_Auto_Increment : boolean := false; -- Modify indexed instr
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BRK_Implements_WAI : boolean := false; -- BRK -> Wait for Int
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BRK_Implements_WAI : boolean := false; -- BRK -> Wait for Int
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Enable_NMI : boolean := true; -- Force INTR0 enabled
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Enable_NMI : boolean := true; -- Force INTR0 enabled
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Sequential_Interrupts : boolean := false; -- Interruptable ISRs
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Sequential_Interrupts : boolean := false; -- Interruptable ISRs
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RTI_Ignores_GP_Flags : boolean := false; -- RTI restores all flags
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RTI_Ignores_GP_Flags : boolean := false; -- RTI sets all flags
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Default_Interrupt_Mask : DATA_TYPE := x"FF"; -- Enable all Ints
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Default_Interrupt_Mask : DATA_TYPE := x"FF"; -- Enable all Ints
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Reset_Level : std_logic := '0' ); -- Active reset level
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Clock_Frequency : real -- Clock Frequency
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);
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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PLL_Locked : in std_logic;
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CPU_Halt : in std_logic := '0';
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CPU_Halt : in std_logic := '0';
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GP_Flags : out EXT_GP_FLAGS;
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--
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--
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Open8_Bus : out OPEN8_BUS_TYPE;
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Open8_Bus : out OPEN8_BUS_TYPE;
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Rd_Data : in DATA_TYPE;
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Rd_Data : in DATA_TYPE;
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Interrupts : in INTERRUPT_BUNDLE := x"00"
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Interrupts : in INTERRUPT_BUNDLE := x"00"
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);
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);
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end entity;
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end entity;
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architecture behave of o8_cpu is
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architecture behave of o8_cpu is
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signal Reset_q : std_logic := Reset_Level;
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signal Reset : std_logic := Reset_Level;
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constant USEC_VAL : integer := integer(Clock_Frequency / 1000000.0);
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constant USEC_WDT : integer := ceil_log2(USEC_VAL - 1);
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constant USEC_DLY : std_logic_vector :=
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conv_std_logic_vector(USEC_VAL - 1, USEC_WDT);
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signal uSec_Cntr : std_logic_vector( USEC_WDT - 1 downto 0 );
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signal uSec_Tick : std_logic;
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constant INT_VECTOR_0 : ADDRESS_TYPE := ISR_Start_Addr;
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constant INT_VECTOR_0 : ADDRESS_TYPE := ISR_Start_Addr;
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constant INT_VECTOR_1 : ADDRESS_TYPE := ISR_Start_Addr+2;
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constant INT_VECTOR_1 : ADDRESS_TYPE := ISR_Start_Addr+2;
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constant INT_VECTOR_2 : ADDRESS_TYPE := ISR_Start_Addr+4;
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constant INT_VECTOR_2 : ADDRESS_TYPE := ISR_Start_Addr+4;
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constant INT_VECTOR_3 : ADDRESS_TYPE := ISR_Start_Addr+6;
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constant INT_VECTOR_3 : ADDRESS_TYPE := ISR_Start_Addr+6;
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constant INT_VECTOR_4 : ADDRESS_TYPE := ISR_Start_Addr+8;
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constant INT_VECTOR_4 : ADDRESS_TYPE := ISR_Start_Addr+8;
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| Line 287... |
Line 299... |
signal Wait_for_FSM : std_logic := '0';
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signal Wait_for_FSM : std_logic := '0';
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signal Wait_for_ISR : std_logic := '0';
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signal Wait_for_ISR : std_logic := '0';
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begin
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begin
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-------------------------------------------------------------------------------
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-- Reset & uSec Tick
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-------------------------------------------------------------------------------
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CPU_Reset_Sync: process( Clock, PLL_Locked )
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begin
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if( PLL_Locked = '0' )then
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Reset_q <= Reset_Level;
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Reset <= Reset_Level;
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elsif( rising_edge(Clock) )then
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Reset_q <= not Reset_Level;
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Reset <= Reset_q;
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end if;
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end process;
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uSec_Tick_proc: process( Clock, Reset )
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begin
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if( Reset = Reset_Level )then
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uSec_Cntr <= USEC_DLY;
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uSec_Tick <= '0';
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elsif( rising_edge( Clock ) )then
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uSec_Cntr <= uSec_Cntr - 1;
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if( or_reduce(uSec_Cntr) = '0' )then
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uSec_Cntr <= USEC_DLY;
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end if;
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uSec_Tick <= nor_reduce(uSec_Cntr);
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end if;
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end process;
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Open8_Bus.Clock <= Clock;
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Open8_Bus.Reset <= Reset;
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Open8_Bus.uSec_Tick <= uSec_Tick;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Address bus selection/generation logic
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-- Address bus selection/generation logic
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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| Line 914... |
Line 958... |
for i in 0 to 7 loop
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for i in 0 to 7 loop
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Regfile(i) <= x"00";
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Regfile(i) <= x"00";
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end loop;
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end loop;
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Flags <= x"00";
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Flags <= x"00";
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GP_Flags <= (others => '0');
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Open8_Bus.GP_Flags <= (others => '0');
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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CPU_Halt_Req <= CPU_Halt;
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CPU_Halt_Req <= CPU_Halt;
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| Line 1251... |
Line 1295... |
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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GP_Flags <= Flags(7 downto 3);
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Open8_Bus.GP_Flags <= Flags(7 downto 3);
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end if;
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end if;
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end process;
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end process;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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