| Line 284... |
Line 284... |
constant USEC_DLY : std_logic_vector :=
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constant USEC_DLY : std_logic_vector :=
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conv_std_logic_vector(USEC_VAL - 1, USEC_WDT);
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conv_std_logic_vector(USEC_VAL - 1, USEC_WDT);
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signal uSec_Cntr : std_logic_vector( USEC_WDT - 1 downto 0 );
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signal uSec_Cntr : std_logic_vector( USEC_WDT - 1 downto 0 );
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signal uSec_Tick : std_logic;
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signal uSec_Tick : std_logic;
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constant INT_VECTOR_0 : ADDRESS_TYPE := ISR_Start_Addr;
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constant INT_VECTOR_1 : ADDRESS_TYPE := ISR_Start_Addr+2;
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constant INT_VECTOR_2 : ADDRESS_TYPE := ISR_Start_Addr+4;
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constant INT_VECTOR_3 : ADDRESS_TYPE := ISR_Start_Addr+6;
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constant INT_VECTOR_4 : ADDRESS_TYPE := ISR_Start_Addr+8;
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constant INT_VECTOR_5 : ADDRESS_TYPE := ISR_Start_Addr+10;
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constant INT_VECTOR_6 : ADDRESS_TYPE := ISR_Start_Addr+12;
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constant INT_VECTOR_7 : ADDRESS_TYPE := ISR_Start_Addr+14;
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signal CPU_Next_State : CPU_STATES := IPF_C0;
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signal CPU_Next_State : CPU_STATES := IPF_C0;
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signal CPU_State : CPU_STATES := IPF_C0;
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signal CPU_State : CPU_STATES := IPF_C0;
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signal CPU_Halt_Req : std_logic := '0';
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signal CPU_Halt_Req : std_logic := '0';
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signal CPU_Halt_Ack : std_logic := '0';
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signal CPU_Halt_Ack : std_logic := '0';
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| Line 327... |
Line 318... |
signal INT_Ctrl : INT_CTRL_TYPE;
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signal INT_Ctrl : INT_CTRL_TYPE;
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signal Ack_D, Ack_Q, Ack_Q1: std_logic := '0';
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signal Ack_D, Ack_Q, Ack_Q1: std_logic := '0';
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signal Int_Req, Int_Ack : std_logic := '0';
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signal Int_Req, Int_Ack : std_logic := '0';
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signal Set_Mask : std_logic := '0';
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signal Set_Mask : std_logic := '0';
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signal Int_Mask : DATA_TYPE := x"00";
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signal Int_Mask : DATA_TYPE := x"00";
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signal ISR_Addr : ADDRESS_TYPE := x"0000";
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signal i_Ints : INTERRUPT_BUNDLE := x"00";
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signal i_Ints : INTERRUPT_BUNDLE := x"00";
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signal Pending : INTERRUPT_BUNDLE := x"00";
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signal Pending : INTERRUPT_BUNDLE := x"00";
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signal Wait_for_FSM : std_logic := '0';
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signal Wait_for_FSM : std_logic := '0';
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signal Wait_for_ISR : std_logic := '0';
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signal Wait_for_ISR : std_logic := '0';
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alias ISR_Addr_Base is ISR_Start_Addr(15 downto 4);
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signal ISR_Addr_Offset : std_logic_vector(3 downto 0) := x"0";
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constant INT_VECTOR_0 : std_logic_vector(3 downto 0) := x"0";
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constant INT_VECTOR_1 : std_logic_vector(3 downto 0) := x"2";
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constant INT_VECTOR_2 : std_logic_vector(3 downto 0) := x"4";
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constant INT_VECTOR_3 : std_logic_vector(3 downto 0) := x"6";
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constant INT_VECTOR_4 : std_logic_vector(3 downto 0) := x"8";
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constant INT_VECTOR_5 : std_logic_vector(3 downto 0) := x"A";
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constant INT_VECTOR_6 : std_logic_vector(3 downto 0) := x"C";
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constant INT_VECTOR_7 : std_logic_vector(3 downto 0) := x"E";
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signal IDX_Offset : ADDRESS_TYPE := x"0000";
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signal IDX_Offset : ADDRESS_TYPE := x"0000";
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signal IDX_Reg_l : integer := 0;
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signal IDX_Reg_l : integer := 0;
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signal IDX_Reg_h : integer := 0;
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signal IDX_Reg_h : integer := 0;
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| Line 380... |
Line 382... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Address bus selection/generation logic
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-- Address bus selection/generation logic
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Address selection logic based on current CPU state. This is combinatorial,
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-- as adding pipeline registration would add a clock cycle to every instr,
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-- without really adding the Fmax to compensate.
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Address_Logic: process(CPU_State, Operand1, Operand2, IDX_NoOffset_Calc,
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IDX_Offset_Calc, ISR_Addr_Offset, Stack_Ptr, Program_Ctr )
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begin
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case( CPU_State )is
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when LDA_C2 | STA_C2 =>
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Open8_Bus.Address <= Operand2 & Operand1;
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when LDX_C1 | STX_C1 =>
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Open8_Bus.Address <= IDX_NoOffset_Calc;
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when LDO_C2 | STO_C2 =>
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Open8_Bus.Address <= IDX_Offset_Calc;
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when ISR_C1 | ISR_C2 =>
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Open8_Bus.Address <= ISR_Addr_Base & ISR_Addr_Offset;
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when PSH_C1 | POP_C1 | ISR_C3 | JSR_C1 | JSR_C2 | RTS_C1 | RTS_C2 | RTS_C3 =>
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Open8_Bus.Address <= Stack_Ptr;
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when others =>
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Open8_Bus.Address <= Program_Ctr;
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end case;
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end process;
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-- The original model treated the offset to LDO/STO as a signed value
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-- The original model treated the offset to LDO/STO as a signed value
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-- allowing access to locations -128 to +127 from [Rn+1:Rn]. This isn't
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-- allowing access to locations -128 to +127 from [Rn+1:Rn]. This isn't
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-- always helpful, so the generic allows the CPU to use unsigned math
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-- always helpful, so the generic allows the CPU to use unsigned math
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-- for the offsets. This makes the range 0 to +255 instead.
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-- for the offsets. This makes the range 0 to +255 instead.
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| Line 423... |
Line 454... |
IDX_Offset_Calc <= (Regfile(IDX_Reg_h) & Regfile(IDX_Reg_l)) +
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IDX_Offset_Calc <= (Regfile(IDX_Reg_h) & Regfile(IDX_Reg_l)) +
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IDX_Offset;
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IDX_Offset;
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end if;
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end if;
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end process;
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end process;
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|
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-- Address selection logic based on current CPU state. This is combinatorial,
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-- as adding pipeline registration would add a clock cycle to every instr,
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-- without really adding the Fmax to compensate.
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Address_Logic: process(CPU_State, Operand1, Operand2, IDX_NoOffset_Calc,
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IDX_Offset_Calc, ISR_Addr, Stack_Ptr, Program_Ctr )
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begin
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case( CPU_State )is
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when LDA_C2 | STA_C2 =>
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Open8_Bus.Address <= Operand2 & Operand1;
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when LDX_C1 | STX_C1 =>
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Open8_Bus.Address <= IDX_NoOffset_Calc;
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when LDO_C2 | STO_C2 =>
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Open8_Bus.Address <= IDX_Offset_Calc;
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when ISR_C1 | ISR_C2 =>
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Open8_Bus.Address <= ISR_Addr;
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when PSH_C1 | POP_C1 | ISR_C3 | JSR_C1 | JSR_C2 | RTS_C1 | RTS_C2 | RTS_C3 =>
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Open8_Bus.Address <= Stack_Ptr;
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when others =>
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Open8_Bus.Address <= Program_Ctr;
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end case;
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end process;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Combinatorial portion of CPU finite state machine
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-- Combinatorial portion of CPU finite state machine
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-- State Logic / Instruction Decoding & Execution
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-- State Logic / Instruction Decoding & Execution
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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| Line 1049... |
Line 1051... |
if( Enable_NMI )then
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if( Enable_NMI )then
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Int_Mask <= Default_Interrupt_Mask(7 downto 1) & '1';
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Int_Mask <= Default_Interrupt_Mask(7 downto 1) & '1';
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else
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else
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Int_Mask <= Default_Interrupt_Mask;
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Int_Mask <= Default_Interrupt_Mask;
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end if;
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end if;
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ISR_Addr <= INT_VECTOR_0;
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ISR_Addr_Offset <= INT_VECTOR_0;
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for i in 0 to 7 loop
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for i in 0 to 7 loop
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Regfile(i) <= x"00";
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Regfile(i) <= x"00";
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end loop;
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end loop;
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Flags <= x"00";
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Flags <= x"00";
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| Line 1212... |
Line 1214... |
Wait_for_ISR <= '0';
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Wait_for_ISR <= '0';
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end if;
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end if;
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if( Wait_for_FSM = '0' and Wait_for_ISR = '0' )then
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if( Wait_for_FSM = '0' and Wait_for_ISR = '0' )then
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if( Pending(0) = '1' )then
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if( Pending(0) = '1' )then
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ISR_Addr <= INT_VECTOR_0;
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ISR_Addr_Offset <= INT_VECTOR_0;
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Pending(0) <= '0';
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Pending(0) <= '0';
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elsif( Pending(1) = '1' )then
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elsif( Pending(1) = '1' )then
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ISR_Addr <= INT_VECTOR_1;
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ISR_Addr_Offset <= INT_VECTOR_1;
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Pending(1) <= '0';
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Pending(1) <= '0';
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elsif( Pending(2) = '1' )then
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elsif( Pending(2) = '1' )then
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ISR_Addr <= INT_VECTOR_2;
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ISR_Addr_Offset <= INT_VECTOR_2;
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Pending(2) <= '0';
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Pending(2) <= '0';
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elsif( Pending(3) = '1' )then
|
elsif( Pending(3) = '1' )then
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ISR_Addr <= INT_VECTOR_3;
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ISR_Addr_Offset <= INT_VECTOR_3;
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Pending(3) <= '0';
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Pending(3) <= '0';
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elsif( Pending(4) = '1' )then
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elsif( Pending(4) = '1' )then
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ISR_Addr <= INT_VECTOR_4;
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ISR_Addr_Offset <= INT_VECTOR_4;
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Pending(4) <= '0';
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Pending(4) <= '0';
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elsif( Pending(5) = '1' )then
|
elsif( Pending(5) = '1' )then
|
ISR_Addr <= INT_VECTOR_5;
|
ISR_Addr_Offset <= INT_VECTOR_5;
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Pending(5) <= '0';
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Pending(5) <= '0';
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elsif( Pending(6) = '1' )then
|
elsif( Pending(6) = '1' )then
|
ISR_Addr <= INT_VECTOR_6;
|
ISR_Addr_Offset <= INT_VECTOR_6;
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Pending(6) <= '0';
|
Pending(6) <= '0';
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elsif( Pending(7) = '1' )then
|
elsif( Pending(7) = '1' )then
|
ISR_Addr <= INT_VECTOR_7;
|
ISR_Addr_Offset <= INT_VECTOR_7;
|
Pending(7) <= '0';
|
Pending(7) <= '0';
|
end if;
|
end if;
|
Wait_for_FSM <= or_reduce(Pending);
|
Wait_for_FSM <= or_reduce(Pending);
|
end if;
|
end if;
|
|
|
| Line 1252... |
Line 1254... |
Int_Req <= Wait_for_FSM and (not Int_Ack);
|
Int_Req <= Wait_for_FSM and (not Int_Ack);
|
|
|
-- Incr_ISR allows the CPU Core to advance the vector address to pop the
|
-- Incr_ISR allows the CPU Core to advance the vector address to pop the
|
-- lower half of the address.
|
-- lower half of the address.
|
if( INT_Ctrl.Incr_ISR = '1' )then
|
if( INT_Ctrl.Incr_ISR = '1' )then
|
ISR_Addr <= ISR_Addr + 1;
|
ISR_Addr_Offset <= ISR_Addr_Offset + 1;
|
end if;
|
end if;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- ALU (Arithmetic / Logic Unit)
|
-- ALU (Arithmetic / Logic Unit)
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
