| Line 256... |
Line 256... |
-- address generator to a multiplexor fed only by
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-- address generator to a multiplexor fed only by
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-- registers.
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-- registers.
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-- Seth Henry 07/10/20 Fixed a bug in the LDO/LDX logic where the register
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-- Seth Henry 07/10/20 Fixed a bug in the LDO/LDX logic where the register
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-- pair wasn't being incremented properly due to a
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-- pair wasn't being incremented properly due to a
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-- missing UPP2 signal to the ALU.
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-- missing UPP2 signal to the ALU.
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-- Seth Henry 10/21/20 Modified the write data path to use separate
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-- enumerated states rather than reuse the .reg field
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-- to improve performance.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 629... |
Line 632... |
ALU_Ctrl.Oper <= ALU_GMSK;
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ALU_Ctrl.Oper <= ALU_GMSK;
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when SOP_JSR =>
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when SOP_JSR =>
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CPU_Next_State <= JSR_C1;
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CPU_Next_State <= JSR_C1;
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Cache_Ctrl <= CACHE_OPER1;
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Cache_Ctrl <= CACHE_OPER1;
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DP_Ctrl.Src <= DATA_WR_PC;
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DP_Ctrl.Src <= DATA_WR_PC_H;
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DP_Ctrl.Reg <= PC_MSB;
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when others => null;
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when others => null;
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end case;
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end case;
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when OP_MUL =>
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when OP_MUL =>
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| Line 977... |
Line 979... |
CPU_Next_State <= JSR_C1;
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CPU_Next_State <= JSR_C1;
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Cache_Ctrl <= CACHE_OPER1;
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Cache_Ctrl <= CACHE_OPER1;
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ALU_Ctrl.Oper <= ALU_STP;
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ALU_Ctrl.Oper <= ALU_STP;
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ALU_Ctrl.Reg <= conv_std_logic_vector(PSR_I,3);
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ALU_Ctrl.Reg <= conv_std_logic_vector(PSR_I,3);
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SP_Ctrl.Oper <= SP_PUSH;
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SP_Ctrl.Oper <= SP_PUSH;
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DP_Ctrl.Src <= DATA_WR_PC;
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DP_Ctrl.Src <= DATA_WR_PC_H;
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DP_Ctrl.Reg <= PC_MSB;
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Ack_D <= '1';
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Ack_D <= '1';
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when JSR_C1 =>
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when JSR_C1 =>
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CPU_Next_State <= JSR_C2;
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CPU_Next_State <= JSR_C2;
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Cache_Ctrl <= CACHE_OPER2;
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Cache_Ctrl <= CACHE_OPER2;
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SP_Ctrl.Oper <= SP_PUSH;
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SP_Ctrl.Oper <= SP_PUSH;
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DP_Ctrl.Src <= DATA_WR_PC;
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DP_Ctrl.Src <= DATA_WR_PC_L;
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DP_Ctrl.Reg <= PC_LSB;
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when JSR_C2 =>
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when JSR_C2 =>
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CPU_Next_State <= IPF_C0;
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CPU_Next_State <= IPF_C0;
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PC_Ctrl.Oper <= PC_LOAD;
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PC_Ctrl.Oper <= PC_LOAD;
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SP_Ctrl.Oper <= SP_PUSH;
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SP_Ctrl.Oper <= SP_PUSH;
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| Line 1196... |
Line 1196... |
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when DATA_WR_FLAG =>
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when DATA_WR_FLAG =>
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Open8_Bus.Wr_En <= '1';
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Open8_Bus.Wr_En <= '1';
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Open8_Bus.Wr_Data <= Flags;
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Open8_Bus.Wr_Data <= Flags;
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when DATA_WR_PC =>
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when DATA_WR_PC_L =>
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Open8_Bus.Wr_En <= '1';
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Open8_Bus.Wr_En <= '1';
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Open8_Bus.Wr_Data <= Program_Ctr(15 downto 8);
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if( DP_Ctrl.Reg = PC_LSB )then
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Open8_Bus.Wr_Data <= Program_Ctr(7 downto 0);
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Open8_Bus.Wr_Data <= Program_Ctr(7 downto 0);
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end if;
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when DATA_WR_PC_H =>
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Open8_Bus.Wr_En <= '1';
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Open8_Bus.Wr_Data <= Program_Ctr(15 downto 8);
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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