| Line 106... |
Line 106... |
-- : behavior treats these offsets as signed values, allowing
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-- : behavior treats these offsets as signed values, allowing
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-- : instructions to offset by -128 to +127 from [Rn+1:Rn].
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-- : instructions to offset by -128 to +127 from [Rn+1:Rn].
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-- : Setting this generic to TRUE will switch to unsigned offsets,
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-- : Setting this generic to TRUE will switch to unsigned offsets,
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-- : switching the range to 0 to 255 instead.
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-- : switching the range to 0 to 255 instead.
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-- :
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-- :
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-- : Rotate_Ignores_Carry alters the ROL and ROR instructions to
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-- : not rotate through, or alter, the carry bit. When enabled,
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-- : ROL performs Rn <= Rn<<1 and ROR performs Rn <= 1>>Rn. Note
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-- : that unlike the original instructions, the C bit is not
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-- : altered.
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-- :
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-- : Default_Interrupt_Mask sets the intial/reset value of the
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-- : Default_Interrupt_Mask sets the intial/reset value of the
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-- : interrupt mask. To remain true to the original core, which
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-- : interrupt mask. To remain true to the original core, which
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-- : had no interrupt mask, this should be set to x"FF". Otherwise
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-- : had no interrupt mask, this should be set to x"FF". Otherwise
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-- : it can be initialized to any value. Note that Enable_NMI
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-- : it can be initialized to any value. Note that Enable_NMI
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-- : will logically force the LSB high.
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-- : will logically force the LSB high.
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| Line 264... |
Line 270... |
-- Seth Henry 10/23/20 Moved CPU internal constants to o8_cpu.vhd. Also
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-- Seth Henry 10/23/20 Moved CPU internal constants to o8_cpu.vhd. Also
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-- removed Stack_Xfer_Flag, which specified the CPU
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-- removed Stack_Xfer_Flag, which specified the CPU
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-- flag used to alter the RSP instruction, making it
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-- flag used to alter the RSP instruction, making it
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-- a constant instead (PSR_GP4). This eliminated the
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-- a constant instead (PSR_GP4). This eliminated the
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-- need to expose an internal constant externally
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-- need to expose an internal constant externally
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-- Seth Henry 05/01/21 Added the Rotate_Ignores_Carry generic, which
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-- alters the ROR and ROL instructions to behave more
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-- like expected by not rotating through the C flag
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|
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 287... |
Line 296... |
Enable_NMI : boolean := true; -- Force INTR0 enabled
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Enable_NMI : boolean := true; -- Force INTR0 enabled
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Sequential_Interrupts : boolean := false; -- Interruptable ISRs
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Sequential_Interrupts : boolean := false; -- Interruptable ISRs
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RTI_Ignores_GP_Flags : boolean := false; -- RTI sets all flags
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RTI_Ignores_GP_Flags : boolean := false; -- RTI sets all flags
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Supervisor_Mode : boolean := false; -- I bit is restricted
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Supervisor_Mode : boolean := false; -- I bit is restricted
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Unsigned_Index_Offsets : boolean := false; -- Offsets are signed
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Unsigned_Index_Offsets : boolean := false; -- Offsets are signed
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Rotate_Ignores_Carry : boolean := false; -- Rotate thru Carry
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Default_Interrupt_Mask : DATA_TYPE := x"FF"; -- Enable all Ints
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Default_Interrupt_Mask : DATA_TYPE := x"FF"; -- Enable all Ints
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Clock_Frequency : real -- Clock Frequency
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Clock_Frequency : real -- Clock Frequency
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);
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);
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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| Line 1557... |
Line 1567... |
Temp(7 downto 0) := Regfile(0) xor Regfile(Index);
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Temp(7 downto 0) := Regfile(0) xor Regfile(Index);
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Flags(PSR_Z) <= nor_reduce(Temp(7 downto 0));
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Flags(PSR_Z) <= nor_reduce(Temp(7 downto 0));
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Flags(PSR_N) <= Temp(7);
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Flags(PSR_N) <= Temp(7);
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Regfile(0) <= Temp(7 downto 0);
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Regfile(0) <= Temp(7 downto 0);
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|
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when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z
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when ALU_ROL => -- Varies based on config
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if( Rotate_Ignores_Carry )then
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-- Rn = Rn<<1 : Flags N,Z
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Temp(7 downto 0) := Regfile(Index)(6 downto 0) & Regfile(Index)(7);
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else
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-- Rn = Rn<<1,C : Flags N,C,Z
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Temp := Regfile(Index) & Flags(PSR_C);
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Temp := Regfile(Index) & Flags(PSR_C);
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Flags(PSR_Z) <= nor_reduce(Temp(7 downto 0));
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Flags(PSR_C) <= Temp(8);
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Flags(PSR_C) <= Temp(8);
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end if;
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Flags(PSR_Z) <= nor_reduce(Temp(7 downto 0));
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Flags(PSR_N) <= Temp(7);
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Flags(PSR_N) <= Temp(7);
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Regfile(Index) <= Temp(7 downto 0);
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Regfile(Index) <= Temp(7 downto 0);
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|
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when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z
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when ALU_ROR => -- Varies based on config
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if( Rotate_Ignores_Carry )then
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|
-- Rn = Rn>>1 : Flags N,Z
|
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Temp(7 downto 0) := Regfile(Index)(0) & Regfile(Index)(7 downto 1);
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|
else
|
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-- Rn = C,Rn>>1 : Flags N,C,Z
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Temp := Regfile(Index)(0) & Flags(PSR_C) &
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Temp := Regfile(Index)(0) & Flags(PSR_C) &
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Regfile(Index)(7 downto 1);
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Regfile(Index)(7 downto 1);
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Flags(PSR_Z) <= nor_reduce(Temp(7 downto 0));
|
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Flags(PSR_C) <= Temp(8);
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Flags(PSR_C) <= Temp(8);
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|
end if;
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Flags(PSR_Z) <= nor_reduce(Temp(7 downto 0));
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Flags(PSR_N) <= Temp(7);
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Flags(PSR_N) <= Temp(7);
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Regfile(Index) <= Temp(7 downto 0);
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Regfile(Index) <= Temp(7 downto 0);
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|
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when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
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when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
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Sum := ("0" & Regfile(Index)) +
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Sum := ("0" & Regfile(Index)) +
|
