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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_cpu.vhd] - Diff between revs 290 and 298

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Rev 290 Rev 298
Line 1... Line 1...
-- Copyright (c)2006, 2011, 2012, 2013, 2015, 2019, 2020 Jeremy Seth Henry
-- Copyright (c)2006, 2011, 2012, 2013, 2015, 2019, 2020, 2022
 
--  Jeremy Seth Henry
-- All rights reserved.
-- All rights reserved.
--
--
-- Redistribution and use in source and binary forms, with or without
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- modification, are permitted provided that the following conditions are met:
--     * Redistributions of source code must retain the above copyright
--     * Redistributions of source code must retain the above copyright
Line 273... Line 274...
--                           a constant instead (PSR_GP4). This eliminated the
--                           a constant instead (PSR_GP4). This eliminated the
--                           need to expose an internal constant externally
--                           need to expose an internal constant externally
-- Seth Henry      05/01/21 Added the Rotate_Ignores_Carry generic, which
-- Seth Henry      05/01/21 Added the Rotate_Ignores_Carry generic, which
--                           alters the ROR and ROL instructions to behave more
--                           alters the ROR and ROL instructions to behave more
--                           like expected by not rotating through the C flag
--                           like expected by not rotating through the C flag
 
-- Seth Henry      07/12/22 Fixed a long-standing bug in the SBC instruction
 
--                           where the 2's complement inversion wasn't adding
 
--                           the additional 1, causing off by 1 errors
 
 
library ieee;
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_arith.all;
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          Flags(PSR_C)       <= Sum(8);
          Flags(PSR_C)       <= Sum(8);
          Flags(PSR_N)       <= Sum(7);
          Flags(PSR_N)       <= Sum(7);
          Regfile(Index)     <= Sum(7 downto 0);
          Regfile(Index)     <= Sum(7 downto 0);
 
 
        when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
        when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
          Sum                := ("0" & Regfile(0)) +
          Sum                := ("0" & Regfile(0)) -
                                ("1" & (not Regfile(Index))) +
                                ("0" & Regfile(Index)) -
                                Flags(PSR_C);
                                Flags(PSR_C);
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
          Flags(PSR_C)       <= Sum(8);
          Flags(PSR_C)       <= Sum(8);
          Flags(PSR_N)       <= Sum(7);
          Flags(PSR_N)       <= Sum(7);
          Regfile(0)         <= Sum(7 downto 0);
          Regfile(0)         <= Sum(7 downto 0);

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