| Line 277... |
Line 277... |
-- alters the ROR and ROL instructions to behave more
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-- alters the ROR and ROL instructions to behave more
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-- like expected by not rotating through the C flag
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-- like expected by not rotating through the C flag
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-- Seth Henry 07/12/22 Fixed a long-standing bug in the SBC instruction
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-- Seth Henry 07/12/22 Fixed a long-standing bug in the SBC instruction
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-- where the 2's complement inversion wasn't adding
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-- where the 2's complement inversion wasn't adding
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-- the additional 1, causing off by 1 errors
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-- the additional 1, causing off by 1 errors
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-- Seth Henry 05/18/23 Removed reset signal from address offset pipeline
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-- registers and cleaned up comments. Also removed
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-- superfluous constant definitions, as they can't
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-- be realistically altered.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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| Line 319... |
Line 323... |
);
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);
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end entity;
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end entity;
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architecture behave of o8_cpu is
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architecture behave of o8_cpu is
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-- The CPU uses the PLL_Locked signal to create an internal reset pulse
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signal Reset_q : std_logic := Reset_Level;
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signal Reset_q : std_logic := Reset_Level;
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signal Reset : std_logic := Reset_Level;
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signal Reset : std_logic := Reset_Level;
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-- Utility 1uS counter signals & constants. Note that the correct clock
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-- frequency is required in Hz. Note that some clock frequencies will not
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-- divide cleanly, producing a slightly fast/slow uSec tick signal
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constant USEC_VAL : integer := integer(Clock_Frequency / 1000000.0);
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constant USEC_VAL : integer := integer(Clock_Frequency / 1000000.0);
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constant USEC_WDT : integer := ceil_log2(USEC_VAL - 1);
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constant USEC_WDT : integer := ceil_log2(USEC_VAL - 1);
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constant USEC_DLY : std_logic_vector :=
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constant USEC_DLY : std_logic_vector :=
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conv_std_logic_vector(USEC_VAL - 1, USEC_WDT);
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conv_std_logic_vector(USEC_VAL - 1, USEC_WDT);
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signal uSec_Cntr : std_logic_vector( USEC_WDT - 1 downto 0 );
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signal uSec_Cntr : std_logic_vector( USEC_WDT - 1 downto 0 );
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| Line 538... |
Line 546... |
signal Wait_for_ISR : std_logic := '0';
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signal Wait_for_ISR : std_logic := '0';
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|
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alias ISR_Addr_Base is ISR_Start_Addr(15 downto 4);
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alias ISR_Addr_Base is ISR_Start_Addr(15 downto 4);
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signal ISR_Addr_Offset : std_logic_vector(3 downto 0) := x"0";
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signal ISR_Addr_Offset : std_logic_vector(3 downto 0) := x"0";
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constant INT_VECTOR_0 : std_logic_vector(3 downto 0) := x"0";
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constant INT_VECTOR_1 : std_logic_vector(3 downto 0) := x"2";
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constant INT_VECTOR_2 : std_logic_vector(3 downto 0) := x"4";
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constant INT_VECTOR_3 : std_logic_vector(3 downto 0) := x"6";
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constant INT_VECTOR_4 : std_logic_vector(3 downto 0) := x"8";
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constant INT_VECTOR_5 : std_logic_vector(3 downto 0) := x"A";
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constant INT_VECTOR_6 : std_logic_vector(3 downto 0) := x"C";
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constant INT_VECTOR_7 : std_logic_vector(3 downto 0) := x"E";
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signal IDX_Offset_SX : std_logic := '0';
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signal IDX_Offset_SX : std_logic := '0';
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|
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signal IDX_Offset : ADDRESS_TYPE := x"0000";
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signal IDX_Offset : ADDRESS_TYPE := x"0000";
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|
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signal IDX_Sel_l : std_logic_vector(2 downto 0) := "000";
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signal IDX_Sel_l : std_logic_vector(2 downto 0) := "000";
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| Line 1260... |
Line 1259... |
if( Enable_NMI )then
|
if( Enable_NMI )then
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Int_Mask <= Default_Interrupt_Mask(7 downto 1) & '1';
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Int_Mask <= Default_Interrupt_Mask(7 downto 1) & '1';
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else
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else
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Int_Mask <= Default_Interrupt_Mask;
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Int_Mask <= Default_Interrupt_Mask;
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end if;
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end if;
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ISR_Addr_Offset <= INT_VECTOR_0;
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ISR_Addr_Offset <= x"0";
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|
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for i in 0 to 7 loop
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for i in 0 to 7 loop
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Regfile(i) <= x"00";
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Regfile(i) <= x"00";
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end loop;
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end loop;
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Flags <= x"00";
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Flags <= x"00";
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| Line 1276... |
Line 1275... |
|
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elsif( rising_edge(Clock) )then
|
elsif( rising_edge(Clock) )then
|
|
|
CPU_State <= CPU_Next_State;
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CPU_State <= CPU_Next_State;
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|
|
|
-------------------------------------------------------------------------------
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-- Register the halt request and acknowledge lines
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-- Register the halt request and acknowledge lines
|
|
-------------------------------------------------------------------------------
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|
|
CPU_Halt_Req <= Halt_Req;
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CPU_Halt_Req <= Halt_Req;
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Halt_Ack <= CPU_Halt_Ack;
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Halt_Ack <= CPU_Halt_Ack;
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|
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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| Line 1457... |
Line 1458... |
Wait_for_ISR <= '0';
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Wait_for_ISR <= '0';
|
end if;
|
end if;
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|
|
if( Wait_for_FSM = '0' and Wait_for_ISR = '0' )then
|
if( Wait_for_FSM = '0' and Wait_for_ISR = '0' )then
|
if( Pending(0) = '1' )then
|
if( Pending(0) = '1' )then
|
ISR_Addr_Offset <= INT_VECTOR_0;
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ISR_Addr_Offset <= x"0";
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Pending(0) <= '0';
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Pending(0) <= '0';
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elsif( Pending(1) = '1' )then
|
elsif( Pending(1) = '1' )then
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ISR_Addr_Offset <= INT_VECTOR_1;
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ISR_Addr_Offset <= x"2";
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Pending(1) <= '0';
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Pending(1) <= '0';
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elsif( Pending(2) = '1' )then
|
elsif( Pending(2) = '1' )then
|
ISR_Addr_Offset <= INT_VECTOR_2;
|
ISR_Addr_Offset <= x"4";
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Pending(2) <= '0';
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Pending(2) <= '0';
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elsif( Pending(3) = '1' )then
|
elsif( Pending(3) = '1' )then
|
ISR_Addr_Offset <= INT_VECTOR_3;
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ISR_Addr_Offset <= x"6";
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Pending(3) <= '0';
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Pending(3) <= '0';
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elsif( Pending(4) = '1' )then
|
elsif( Pending(4) = '1' )then
|
ISR_Addr_Offset <= INT_VECTOR_4;
|
ISR_Addr_Offset <= x"8";
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Pending(4) <= '0';
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Pending(4) <= '0';
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elsif( Pending(5) = '1' )then
|
elsif( Pending(5) = '1' )then
|
ISR_Addr_Offset <= INT_VECTOR_5;
|
ISR_Addr_Offset <= x"A";
|
Pending(5) <= '0';
|
Pending(5) <= '0';
|
elsif( Pending(6) = '1' )then
|
elsif( Pending(6) = '1' )then
|
ISR_Addr_Offset <= INT_VECTOR_6;
|
ISR_Addr_Offset <= x"C";
|
Pending(6) <= '0';
|
Pending(6) <= '0';
|
elsif( Pending(7) = '1' )then
|
elsif( Pending(7) = '1' )then
|
ISR_Addr_Offset <= INT_VECTOR_7;
|
ISR_Addr_Offset <= x"E";
|
Pending(7) <= '0';
|
Pending(7) <= '0';
|
end if;
|
end if;
|
Wait_for_FSM <= or_reduce(Pending);
|
Wait_for_FSM <= or_reduce(Pending);
|
end if;
|
end if;
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