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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_crc16_ccitt.vhd] - Diff between revs 180 and 191

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Rev 180 Rev 191
Line 105... Line 105...
 
 
  CRC16_Calc: process( Clock, Reset )
  CRC16_Calc: process( Clock, Reset )
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      Reg_Sel                <= "00";
      Reg_Sel                <= "00";
      Rd_En                  <= '0';
 
      Rd_Data                <= x"00";
 
      Wr_En                  <= '0';
      Wr_En                  <= '0';
      Wr_Data_q              <= x"00";
      Wr_Data_q              <= x"00";
 
      Rd_En                  <= '0';
 
      Rd_Data                <= OPEN8_NULLBUS;
 
 
      Byte_Count             <= x"00";
      Byte_Count             <= x"00";
      Calc_En                <= '0';
      Calc_En                <= '0';
      Buffer_En              <= '0';
      Buffer_En              <= '0';
      Data                   <= x"00";
      Data                   <= x"00";
      Reg                    <= x"0000";
      Reg                    <= x"0000";
    elsif( rising_edge(Clock) )then
    elsif( rising_edge(Clock) )then
      Rd_Data                <= (others => '0');
 
      Rd_En                  <= Addr_Match and Rd_Enable;
 
      Wr_En                  <= Addr_Match and Wr_Enable;
 
      Wr_Data_q              <= Wr_Data;
 
      Reg_Sel                <= Reg_Addr;
      Reg_Sel                <= Reg_Addr;
 
 
      Calc_En                <= '0';
      Wr_En                  <= Addr_Match and Wr_Enable;
      Buffer_En              <= Calc_En;
      Wr_Data_q              <= Wr_Data;
 
 
      if( Calc_En = '1' )then
 
        Reg(0)               <= Reg(8)  xor            Exr(4) xor Exr(0);
 
        Reg(1)               <= Reg(9)  xor            Exr(5) xor Exr(1);
 
        Reg(2)               <= Reg(10) xor            Exr(6) xor Exr(2);
 
        Reg(3)               <= Reg(11) xor Exr(0) xor Exr(7) xor Exr(3);
 
        Reg(4)               <= Reg(12) xor Exr(1)                      ;
 
        Reg(5)               <= Reg(13) xor Exr(2)                      ;
 
        Reg(6)               <= Reg(14) xor Exr(3)                      ;
 
        Reg(7)               <= Reg(15) xor Exr(4)            xor Exr(0);
 
        Reg(8)               <= Exr(0)  xor Exr(5)            xor Exr(1);
 
        Reg(9)               <= Exr(1)  xor Exr(6)            xor Exr(2);
 
        Reg(10)              <= Exr(2)  xor Exr(7)            xor Exr(3);
 
        Reg(11)              <= Exr(3)                                  ;
 
        Reg(12)              <= Exr(4)                        xor Exr(0);
 
        Reg(13)              <= Exr(5)                        xor Exr(1);
 
        Reg(14)              <= Exr(6)                        xor Exr(2);
 
        Reg(15)              <= Exr(7)                        xor Exr(3);
 
      end if;
 
 
 
      if( Buffer_En = '1' )then
 
        Byte_Count           <= Byte_Count + 1;
 
        Comp_Data            <= Reg xor x"FFFF";
 
      end if;
 
 
 
      if( Wr_En = '1' )then
      if( Wr_En = '1' )then
        case( Reg_Sel )is
        case( Reg_Sel )is
          when "00" => -- Load next byte
          when "00" => -- Load next byte
            Data             <= Wr_Data_q;
            Data             <= Wr_Data_q;
Line 163... Line 135...
 
 
          when others => null;
          when others => null;
        end case;
        end case;
      end if;
      end if;
 
 
 
      Rd_En                  <= Addr_Match and Rd_Enable;
 
      Rd_Data                <= OPEN8_NULLBUS;
      if( Rd_En = '1' )then
      if( Rd_En = '1' )then
        case( Reg_Sel )is
        case( Reg_Sel )is
          when "00" => -- Read last byte
          when "00" => -- Read last byte
            Rd_Data          <= Data;
            Rd_Data          <= Data;
 
 
Line 181... Line 155...
 
 
          when others => null;
          when others => null;
        end case;
        end case;
      end if;
      end if;
 
 
 
      Calc_En                <= '0';
 
      Buffer_En              <= Calc_En;
 
 
 
      if( Calc_En = '1' )then
 
        Reg(0)               <= Reg(8)  xor            Exr(4) xor Exr(0);
 
        Reg(1)               <= Reg(9)  xor            Exr(5) xor Exr(1);
 
        Reg(2)               <= Reg(10) xor            Exr(6) xor Exr(2);
 
        Reg(3)               <= Reg(11) xor Exr(0) xor Exr(7) xor Exr(3);
 
        Reg(4)               <= Reg(12) xor Exr(1)                      ;
 
        Reg(5)               <= Reg(13) xor Exr(2)                      ;
 
        Reg(6)               <= Reg(14) xor Exr(3)                      ;
 
        Reg(7)               <= Reg(15) xor Exr(4)            xor Exr(0);
 
        Reg(8)               <= Exr(0)  xor Exr(5)            xor Exr(1);
 
        Reg(9)               <= Exr(1)  xor Exr(6)            xor Exr(2);
 
        Reg(10)              <= Exr(2)  xor Exr(7)            xor Exr(3);
 
        Reg(11)              <= Exr(3)                                  ;
 
        Reg(12)              <= Exr(4)                        xor Exr(0);
 
        Reg(13)              <= Exr(5)                        xor Exr(1);
 
        Reg(14)              <= Exr(6)                        xor Exr(2);
 
        Reg(15)              <= Exr(7)                        xor Exr(3);
 
      end if;
 
 
 
      if( Buffer_En = '1' )then
 
        Byte_Count           <= Byte_Count + 1;
 
        Comp_Data            <= Reg xor x"FFFF";
 
      end if;
 
 
    end if;
    end if;
  end process;
  end process;
 
 
end architecture;
end architecture;
 
 
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