| Line 66... |
Line 66... |
);
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);
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end entity;
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end entity;
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architecture behave of o8_crc16_ccitt is
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architecture behave of o8_crc16_ccitt is
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constant Poly_Init : std_logic_vector(15 downto 0) := x"0000";
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constant Poly_Init : std_logic_vector(15 downto 0) :=
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(others => '0');
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constant User_Addr : std_logic_vector(15 downto 2)
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constant User_Addr : std_logic_vector(15 downto 2)
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:= Address(15 downto 2);
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:= Address(15 downto 2);
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alias Comp_Addr is Bus_Address(15 downto 2);
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alias Comp_Addr is Bus_Address(15 downto 2);
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alias Reg_Addr is Bus_Address(1 downto 0);
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alias Reg_Addr is Bus_Address(1 downto 0);
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signal Reg_Sel : std_logic_vector(1 downto 0);
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signal Reg_Sel : std_logic_vector(1 downto 0) :=
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(others => '0');
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic;
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signal Wr_En : std_logic;
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signal Wr_En : std_logic;
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signal Wr_Data_q : DATA_TYPE;
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signal Wr_Data_q : DATA_TYPE := (others => '0');
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signal Rd_En : std_logic;
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signal Rd_En : std_logic;
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signal Next_Byte : DATA_TYPE;
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signal Next_Byte : DATA_TYPE := (others => '0');
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signal Byte_Count : DATA_TYPE;
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signal Byte_Count : DATA_TYPE := (others => '0');
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signal Calc_En : std_logic;
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signal Calc_En : std_logic := '0';
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signal Buffer_En : std_logic;
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signal Buffer_En : std_logic := '0';
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signal Data : DATA_TYPE;
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signal Data : DATA_TYPE := (others => '0');
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signal Exr : DATA_TYPE;
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signal Exr : DATA_TYPE := (others => '0');
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signal Reg : std_logic_vector(15 downto 0);
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signal Reg : std_logic_vector(15 downto 0) :=
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signal Comp_Data : std_logic_vector(15 downto 0);
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(others => '0');
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signal Comp_Data : std_logic_vector(15 downto 0) :=
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(others => '0');
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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