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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_crc16_ccitt.vhd] - Diff between revs 224 and 244

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Rev 224 Rev 244
Line 40... Line 40...
-- Revision History
-- Revision History
-- Author          Date     Change
-- Author          Date     Change
------------------ -------- ---------------------------------------------------
------------------ -------- ---------------------------------------------------
-- Seth Henry      12/19/19 Design Start
-- Seth Henry      12/19/19 Design Start
-- Seth Henry      04/16/20 Modified to use Open8 bus record
-- Seth Henry      04/16/20 Modified to use Open8 bus record
 
-- Seth Henry      05/18/20 Added write qualification input
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
 
 
Line 54... Line 55...
generic(
generic(
  Address                    : ADDRESS_TYPE
  Address                    : ADDRESS_TYPE
);
);
port(
port(
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
 
  Write_Qual                 : in  std_logic := '1';
  Rd_Data                    : out DATA_TYPE
  Rd_Data                    : out DATA_TYPE
);
);
end entity;
end entity;
 
 
architecture behave of o8_crc16_ccitt is
architecture behave of o8_crc16_ccitt is
Line 69... Line 71...
                                (others => '0');
                                (others => '0');
 
 
  constant User_Addr         : std_logic_vector(15 downto 2)
  constant User_Addr         : std_logic_vector(15 downto 2)
                               := Address(15 downto 2);
                               := Address(15 downto 2);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
  alias  Reg_Addr            is Open8_Bus.Address(1 downto 0);
 
  signal Reg_Sel             : std_logic_vector(1 downto 0) :=
 
                               (others => '0');
 
  signal Addr_Match          : std_logic;
  signal Addr_Match          : std_logic;
  signal Wr_En               : std_logic;
 
  signal Wr_Data_q           : DATA_TYPE := (others => '0');
  alias  Reg_Sel_d           is Open8_Bus.Address(1 downto 0);
  signal Rd_En               : std_logic;
  signal Reg_Sel_q           : std_logic_vector(1 downto 0) := "00";
 
  signal Wr_En_d             : std_logic := '0';
 
  signal Wr_En_q             : std_logic := '0';
 
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
 
  signal Wr_Data_q           : DATA_TYPE := x"00";
 
  signal Rd_En_d             : std_logic := '0';
 
  signal Rd_En_q             : std_logic := '0';
 
 
  signal Next_Byte           : DATA_TYPE := (others => '0');
  signal Next_Byte           : DATA_TYPE := (others => '0');
  signal Byte_Count          : DATA_TYPE := (others => '0');
  signal Byte_Count          : DATA_TYPE := (others => '0');
 
 
  signal Calc_En             : std_logic := '0';
  signal Calc_En             : std_logic := '0';
Line 92... Line 97...
                                (others => '0');
                                (others => '0');
 
 
begin
begin
 
 
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
 
  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
 
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
 
 
  Exr(0)                     <= Reg(0) xor Data(0);
  Exr(0)                     <= Reg(0) xor Data(0);
  Exr(1)                     <= Reg(1) xor Data(1);
  Exr(1)                     <= Reg(1) xor Data(1);
  Exr(2)                     <= Reg(2) xor Data(2);
  Exr(2)                     <= Reg(2) xor Data(2);
  Exr(3)                     <= Reg(3) xor Data(3);
  Exr(3)                     <= Reg(3) xor Data(3);
Line 105... Line 112...
  Exr(7)                     <= Reg(7) xor Data(7);
  Exr(7)                     <= Reg(7) xor Data(7);
 
 
  CRC16_Calc: process( Clock, Reset )
  CRC16_Calc: process( Clock, Reset )
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      Reg_Sel                <= "00";
      Reg_Sel_q              <= "00";
      Wr_En                  <= '0';
      Wr_En_q                <= '0';
      Wr_Data_q              <= x"00";
      Wr_Data_q              <= x"00";
      Rd_En                  <= '0';
      Rd_En_q                <= '0';
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
 
 
      Byte_Count             <= x"00";
      Byte_Count             <= x"00";
      Calc_En                <= '0';
      Calc_En                <= '0';
      Buffer_En              <= '0';
      Buffer_En              <= '0';
      Data                   <= x"00";
      Data                   <= x"00";
      Reg                    <= x"0000";
      Reg                    <= x"0000";
    elsif( rising_edge(Clock) )then
    elsif( rising_edge(Clock) )then
      Reg_Sel                <= Reg_Addr;
      Reg_Sel_q              <= Reg_Sel_d;
 
 
      Wr_En                  <= Addr_Match and Open8_Bus.Wr_En;
      Wr_En_q                <= Wr_En_d;
      Wr_Data_q              <= Open8_Bus.Wr_Data;
      Wr_Data_q              <= Wr_Data_d;
 
 
      if( Wr_En = '1' )then
      if( Wr_En_q = '1' )then
        case( Reg_Sel )is
        case( Reg_Sel_q )is
          when "00" => -- Load next byte
          when "00" => -- Load next byte
            Data             <= Wr_Data_q;
            Data             <= Wr_Data_q;
            Calc_En          <= '1';
            Calc_En          <= '1';
 
 
          when "01" => -- Clear accumulator and byte counter
          when "01" => -- Clear accumulator and byte counter
Line 136... Line 143...
 
 
          when others => null;
          when others => null;
        end case;
        end case;
      end if;
      end if;
 
 
      Rd_En                  <= Addr_Match and Open8_Bus.Rd_En;
      Rd_En_q                <= Rd_En_d;
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
      if( Rd_En = '1' )then
      if( Rd_En_q = '1' )then
        case( Reg_Sel )is
        case( Reg_Sel_q )is
          when "00" => -- Read last byte
          when "00" => -- Read last byte
            Rd_Data          <= Data;
            Rd_Data          <= Data;
 
 
          when "01" => -- Read the byte counter
          when "01" => -- Read the byte counter
            Rd_Data          <= Byte_Count;
            Rd_Data          <= Byte_Count;

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