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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_datalatch.vhd] - Diff between revs 224 and 244

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Rev 224 Rev 244
Line 63... Line 63...
  alias Clock                is Open8_Bus.Clock;
  alias Clock                is Open8_Bus.Clock;
  alias Reset                is Open8_Bus.Reset;
  alias Reset                is Open8_Bus.Reset;
 
 
  constant User_Addr         : std_logic_vector(15 downto 0) := Address;
  constant User_Addr         : std_logic_vector(15 downto 0) := Address;
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 0);
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 0);
  signal Addr_Match          : std_logic;
  signal Addr_Match          : std_logic := '0';
  signal Rd_En               : std_logic;
 
 
 
  signal Strobe_sr           : std_logic_vector(3 downto 0);
  signal Rd_En_d             : std_logic := '0';
  signal Strobe_re           : std_logic;
  signal Rd_En_q             : std_logic := '0';
 
 
  signal LData_q1            : DATA_TYPE;
  signal Strobe_sr           : std_logic_vector(3 downto 0) := "0000";
  signal LData_q2            : DATA_TYPE;
  signal Strobe_re           : std_logic := '0';
  signal LData_q3            : DATA_TYPE;
 
 
  signal LData_q1            : DATA_TYPE := x"00";
 
  signal LData_q2            : DATA_TYPE := x"00";
 
  signal LData_q3            : DATA_TYPE := x"00";
 
 
begin
begin
 
 
  Addr_Match                 <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else '0';
  Addr_Match                 <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else '0';
  Strobe_re                  <= Strobe_sr(2) and not Strobe_sr(3);
  Strobe_re                  <= Strobe_sr(2) and not Strobe_sr(3);
 
 
  io_reg: process( Clock, Reset )
  io_reg: process( Clock, Reset )
  begin
  begin
    if( Reset = Reset_Level )then
    if( Reset = Reset_Level )then
      Rd_En                  <= '0';
      Rd_En_q                <= '0';
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
      Strobe_sr              <= (others => '0');
      Strobe_sr              <= (others => '0');
      Interrupt              <= '0';
      Interrupt              <= '0';
      LData_q1               <= x"00";
      LData_q1               <= x"00";
      LData_q2               <= x"00";
      LData_q2               <= x"00";
Line 99... Line 101...
      if( Strobe_re = '1' )then
      if( Strobe_re = '1' )then
        LData_q3             <= LData_q2;
        LData_q3             <= LData_q2;
      end if;
      end if;
 
 
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_Data                <= OPEN8_NULLBUS;
      Rd_En                  <= Addr_Match;
      Rd_En_q                <= Rd_En_d;
      if( Rd_En = '1' )then
      if( Rd_En_q = '1' )then
        Rd_Data              <= LData_q3;
        Rd_Data              <= LData_q3;
      end if;
      end if;
    end if;
    end if;
  end process;
  end process;
 
 

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