URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_datalatch.vhd] - Diff between revs 180 and 191
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 180 |
Rev 191 |
| Line 83... |
Line 83... |
|
|
io_reg: process( Clock, Reset )
|
io_reg: process( Clock, Reset )
|
begin
|
begin
|
if( Reset = Reset_Level )then
|
if( Reset = Reset_Level )then
|
Rd_En <= '0';
|
Rd_En <= '0';
|
Rd_Data <= x"00";
|
Rd_Data <= OPEN8_NULLBUS;
|
Strobe_sr <= (others => '0');
|
Strobe_sr <= (others => '0');
|
Interrupt <= '0';
|
Interrupt <= '0';
|
LData_q1 <= x"00";
|
LData_q1 <= x"00";
|
LData_q2 <= x"00";
|
LData_q2 <= x"00";
|
LData_q3 <= x"00";
|
LData_q3 <= x"00";
|
| Line 99... |
Line 99... |
Interrupt <= Strobe_re;
|
Interrupt <= Strobe_re;
|
if( Strobe_re = '1' )then
|
if( Strobe_re = '1' )then
|
LData_q3 <= LData_q2;
|
LData_q3 <= LData_q2;
|
end if;
|
end if;
|
|
|
Rd_Data <= (others => '0');
|
Rd_Data <= OPEN8_NULLBUS;
|
Rd_En <= Addr_Match;
|
Rd_En <= Addr_Match;
|
if( Rd_En = '1' )then
|
if( Rd_En = '1' )then
|
Rd_Data <= LData_q3;
|
Rd_Data <= LData_q3;
|
end if;
|
end if;
|
end if;
|
end if;
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.