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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_datalatch.vhd] - Diff between revs 217 and 223

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Rev 217 Rev 223
Line 50... Line 50... 
);
 
);
 
port(
 
port(
 
  Clock                      : in  std_logic;
 
  Clock                      : in  std_logic;
 
  Reset                      : in  std_logic;
 
  Reset                      : in  std_logic;
 
  --
 
  --
 
  Bus_Address                : in  ADDRESS_TYPE;
 
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
 
  Rd_Enable                  : in  std_logic;
 
 
 
  Rd_Data                    : out DATA_TYPE;
 
  Rd_Data                    : out DATA_TYPE;
 
  Interrupt                  : out std_logic;
 
  Interrupt                  : out std_logic;
 
  --
 
  --
 
  L_Strobe                   : in  std_logic;
 
  L_Strobe                   : in  std_logic;
 
  L_Data                     : in  DATA_TYPE
 
  L_Data                     : in  DATA_TYPE
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end entity;
 
end entity;
 
 
 
 
 
architecture behave of o8_datalatch is
 
architecture behave of o8_datalatch is
 
 
 
 
 
  constant User_Addr         : std_logic_vector(15 downto 0) := Address;
 
  constant User_Addr         : std_logic_vector(15 downto 0) := Address;
 
  alias  Comp_Addr           is Bus_Address(15 downto 0);
 
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 0);
 
  signal Addr_Match          : std_logic;
 
  signal Addr_Match          : std_logic;
 
  signal Rd_En               : std_logic;
 
  signal Rd_En               : std_logic;
 
 
 
 
 
  signal Strobe_sr           : std_logic_vector(3 downto 0);
 
  signal Strobe_sr           : std_logic_vector(3 downto 0);
 
  signal Strobe_re           : std_logic;
 
  signal Strobe_re           : std_logic;
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  signal LData_q2            : DATA_TYPE;
 
  signal LData_q2            : DATA_TYPE;
 
  signal LData_q3            : DATA_TYPE;
 
  signal LData_q3            : DATA_TYPE;
 
 
 
 
 
begin
 
begin
 
 
 
 
 
  Addr_Match                 <= Rd_Enable when Comp_Addr = User_Addr else '0';
 
  Addr_Match                 <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else '0';
 
  Strobe_re                  <= Strobe_sr(2) and not Strobe_sr(3);
 
  Strobe_re                  <= Strobe_sr(2) and not Strobe_sr(3);
 
 
 
 
 
  io_reg: process( Clock, Reset )
 
  io_reg: process( Clock, Reset )
 
  begin
 
  begin
 
    if( Reset = Reset_Level )then
 
    if( Reset = Reset_Level )then

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