| Line 63... |
Line 63... |
alias Clock is Open8_Bus.Clock;
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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alias Reset is Open8_Bus.Reset;
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constant User_Addr : std_logic_vector(15 downto 0) := Address;
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constant User_Addr : std_logic_vector(15 downto 0) := Address;
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alias Comp_Addr is Open8_Bus.Address(15 downto 0);
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alias Comp_Addr is Open8_Bus.Address(15 downto 0);
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signal Addr_Match : std_logic;
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signal Addr_Match : std_logic := '0';
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signal Rd_En : std_logic;
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signal Strobe_sr : std_logic_vector(3 downto 0);
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signal Rd_En_d : std_logic := '0';
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signal Strobe_re : std_logic;
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signal Rd_En_q : std_logic := '0';
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signal LData_q1 : DATA_TYPE;
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signal Strobe_sr : std_logic_vector(3 downto 0) := "0000";
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signal LData_q2 : DATA_TYPE;
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signal Strobe_re : std_logic := '0';
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signal LData_q3 : DATA_TYPE;
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signal LData_q1 : DATA_TYPE := x"00";
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signal LData_q2 : DATA_TYPE := x"00";
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signal LData_q3 : DATA_TYPE := x"00";
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begin
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begin
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Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else '0';
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Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else '0';
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Strobe_re <= Strobe_sr(2) and not Strobe_sr(3);
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Strobe_re <= Strobe_sr(2) and not Strobe_sr(3);
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Rd_En <= '0';
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Rd_En_q <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Strobe_sr <= (others => '0');
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Strobe_sr <= (others => '0');
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Interrupt <= '0';
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Interrupt <= '0';
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LData_q1 <= x"00";
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LData_q1 <= x"00";
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LData_q2 <= x"00";
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LData_q2 <= x"00";
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| Line 99... |
Line 101... |
if( Strobe_re = '1' )then
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if( Strobe_re = '1' )then
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LData_q3 <= LData_q2;
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LData_q3 <= LData_q2;
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end if;
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end if;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En <= Addr_Match;
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Rd_En_q <= Rd_En_d;
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if( Rd_En = '1' )then
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if( Rd_En_q = '1' )then
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Rd_Data <= LData_q3;
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Rd_Data <= LData_q3;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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