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https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_de0_nano_adc_if.vhd] - Diff between revs 315 and 317
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Rev 317 |
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Line 81... |
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alias Clock is Open8_Bus.Clock;
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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alias Reset is Open8_Bus.Reset;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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signal Reinit : std_logic := '0';
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signal RAW_Channel : std_logic_vector(2 downto 0) := (others => '0');
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signal RAW_Channel : std_logic_vector(2 downto 0) := (others => '0');
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signal RAW_Data : std_logic_vector(15 downto 0) := (others => '0');
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signal RAW_Data : std_logic_vector(15 downto 0) := (others => '0');
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signal RAW_Valid : std_logic := '0';
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signal RAW_Valid : std_logic := '0';
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signal AVG_Busy : std_logic := '0';
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signal AVG_Busy : std_logic := '0';
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)
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)
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port map(
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port map(
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Clock => Clock,
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Clock => Clock,
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Reset => Reset,
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Reset => Reset,
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--
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--
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Reinit => Reinit,
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--
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RAW_Channel => RAW_Channel,
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RAW_Channel => RAW_Channel,
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RAW_Data => RAW_Data,
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RAW_Data => RAW_Data,
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RAW_Valid => RAW_Valid,
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RAW_Valid => RAW_Valid,
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--
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--
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Busy_In => AVG_Busy,
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Busy_In => AVG_Busy,
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