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-- Copyright (c)2013 Jeremy Seth Henry
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-- Copyright (c)2011, 2019 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x0 AAAAAAAA B0 of Setpoint (W) or Buffered Time(R)
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-- 0x0 AAAAAAAA B0 of Setpoint (W) or Buffered Time(R)
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-- 0x1 AAAAAAAA B1 of Setpoint (W) or Buffered Time(R)
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-- 0x1 AAAAAAAA B1 of Setpoint (W) or Buffered Time(R)
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-- 0x2 AAAAAAAA B2 of Setpoint (W) or Buffered Time(R)
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-- 0x2 AAAAAAAA B2 of Setpoint (W) or Buffered Time(R)
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-- 0x3 DC----BA Control/Status register (RW)
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-- 0x3 C-----BA Control/Status register (RW)
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-- A = Update Buffered Time from internal timer (W)
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-- A = Update Buffered Time from internal timer (W)
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-- B = Reset Internal Epoch Time (W)
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-- B = Reset Internal Epoch Time (W)
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-- C = Interrupt Enable (RW)
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-- C = Alarm State Flag (RW) (write a 1 to clear)
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-- D = Alarm State Flag (RW) (write a 1 to clear)
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--
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-- Revision History
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 07/28/11 Design Start
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-- Seth Henry 12/19/19 Renamed to "o8_epoch_timer" to fit "theme"
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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signal epoch_buffer : std_logic_vector(23 downto 0);
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signal epoch_buffer : std_logic_vector(23 downto 0);
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signal epoch_setpt : std_logic_vector(25 downto 0);
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signal epoch_setpt : std_logic_vector(25 downto 0);
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signal epoch_alarm : std_logic;
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signal epoch_alarm : std_logic;
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signal epoch_alarm_q : std_logic;
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signal epoch_alarm_q : std_logic;
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signal epoch_gie : std_logic;
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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Wr_Data_q <= (others => '0');
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Wr_Data_q <= (others => '0');
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Reg_Addr_q <= (others => '0');
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Reg_Addr_q <= (others => '0');
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Wr_En <= '0';
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Wr_En <= '0';
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= (others => '0');
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Rd_Data <= (others => '0');
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epoch_gie <= '0';
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Interrupt <= '0';
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Interrupt <= '0';
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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epoch_tmr <= epoch_tmr + uSec_Tick;
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epoch_tmr <= epoch_tmr + uSec_Tick;
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-- Force the lower bits of the setpoint to "11" so that the offset is
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-- Force the lower bits of the setpoint to "11" so that the offset is
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-- reduced to 1uS (reproducing the original behavior). Software should
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-- reduced to 1uS (reproducing the original behavior). Software should
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epoch_buffer <= epoch_tmrcmp;
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epoch_buffer <= epoch_tmrcmp;
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end if;
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end if;
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if( Wr_Data_q(1) = '1' )then
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if( Wr_Data_q(1) = '1' )then
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epoch_tmr <= (others => '0');
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epoch_tmr <= (others => '0');
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end if;
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end if;
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epoch_gie <= Wr_Data_q(6);
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if( Wr_Data_q(7) = '1' )then
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if( Wr_Data_q(7) = '1' )then
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epoch_alarm <= '0';
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epoch_alarm <= '0';
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end if;
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end if;
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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-- Set and hold on alarm condition
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-- Set and hold on alarm condition
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if( (epoch_tmr > epoch_setpt) and (epoch_alarm = '0') )then
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if( epoch_tmr > epoch_setpt )then
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epoch_alarm <= '1';
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epoch_alarm <= '1';
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end if;
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end if;
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epoch_alarm_q <= epoch_alarm;
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epoch_alarm_q <= epoch_alarm;
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-- Fire on rising edge of epoch_alarm
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-- Fire on rising edge of epoch_alarm
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Interrupt <= epoch_gie and
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Interrupt <= epoch_alarm and not epoch_alarm_q;
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(epoch_alarm and not epoch_alarm_q);
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Rd_Data <= (others => '0');
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Rd_Data <= (others => '0');
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Rd_En <= Addr_Match and Rd_Enable;
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Rd_En <= Addr_Match and Rd_Enable;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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case( Reg_Addr_q )is
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case( Reg_Addr_q )is
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when "01" =>
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when "01" =>
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Rd_Data <= epoch_buffer(15 downto 8);
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Rd_Data <= epoch_buffer(15 downto 8);
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when "10" =>
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when "10" =>
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Rd_Data <= epoch_buffer(23 downto 16);
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Rd_Data <= epoch_buffer(23 downto 16);
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when "11" =>
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when "11" =>
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Rd_Data <= epoch_alarm & epoch_gie &
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Rd_Data <= epoch_alarm & "0000000";
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"000000";
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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