URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_epoch_timer.vhd] - Diff between revs 194 and 209
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 194 |
Rev 209 |
| Line 115... |
Line 115... |
epoch_tmr <= epoch_tmr + uSec_Tick;
|
epoch_tmr <= epoch_tmr + uSec_Tick;
|
-- Force the lower bits of the setpoint to "11" so that the offset is
|
-- Force the lower bits of the setpoint to "11" so that the offset is
|
-- reduced to 1uS (reproducing the original behavior). Software should
|
-- reduced to 1uS (reproducing the original behavior). Software should
|
-- always subtract 4uS (-1) from the desired time to compensate
|
-- always subtract 4uS (-1) from the desired time to compensate
|
epoch_setpt(1 downto 0) <= "11";
|
epoch_setpt(1 downto 0) <= "11";
|
|
if( epoch_setpt(25 downto 2) = 0 )then
|
|
epoch_setpt(1 downto 0) <= "00";
|
|
end if;
|
|
|
Reg_Addr_q <= Reg_Addr;
|
Reg_Addr_q <= Reg_Addr;
|
Wr_Data_q <= Wr_Data;
|
Wr_Data_q <= Wr_Data;
|
|
|
Wr_En <= Addr_Match and Wr_Enable;
|
Wr_En <= Addr_Match and Wr_Enable;
|
if( Wr_En = '1' and or_reduce(Reg_Addr_q) = '0' )then
|
if( Wr_En = '1' and or_reduce(Reg_Addr_q) = '0' )then
|
| Line 147... |
Line 151... |
when others => null;
|
when others => null;
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
-- Set and hold on alarm condition
|
-- Set and hold on alarm condition
|
if( epoch_tmr > epoch_setpt )then
|
if( epoch_tmr > epoch_setpt and epoch_setpt > 0 )then
|
epoch_alarm <= '1';
|
epoch_alarm <= '1';
|
end if;
|
end if;
|
|
|
epoch_alarm_q <= epoch_alarm;
|
epoch_alarm_q <= epoch_alarm;
|
-- Fire on rising edge of epoch_alarm
|
-- Fire on rising edge of epoch_alarm
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.