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https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_epoch_timer.vhd] - Diff between revs 194 and 209
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| Rev 194 |
Rev 209 |
| Line 115... |
Line 115... |
epoch_tmr <= epoch_tmr + uSec_Tick;
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epoch_tmr <= epoch_tmr + uSec_Tick;
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-- Force the lower bits of the setpoint to "11" so that the offset is
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-- Force the lower bits of the setpoint to "11" so that the offset is
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-- reduced to 1uS (reproducing the original behavior). Software should
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-- reduced to 1uS (reproducing the original behavior). Software should
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-- always subtract 4uS (-1) from the desired time to compensate
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-- always subtract 4uS (-1) from the desired time to compensate
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epoch_setpt(1 downto 0) <= "11";
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epoch_setpt(1 downto 0) <= "11";
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if( epoch_setpt(25 downto 2) = 0 )then
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epoch_setpt(1 downto 0) <= "00";
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end if;
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Reg_Addr_q <= Reg_Addr;
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Reg_Addr_q <= Reg_Addr;
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Wr_Data_q <= Wr_Data;
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Wr_Data_q <= Wr_Data;
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Wr_En <= Addr_Match and Wr_Enable;
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Wr_En <= Addr_Match and Wr_Enable;
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if( Wr_En = '1' and or_reduce(Reg_Addr_q) = '0' )then
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if( Wr_En = '1' and or_reduce(Reg_Addr_q) = '0' )then
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| Line 147... |
Line 151... |
when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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-- Set and hold on alarm condition
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-- Set and hold on alarm condition
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if( epoch_tmr > epoch_setpt )then
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if( epoch_tmr > epoch_setpt and epoch_setpt > 0 )then
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epoch_alarm <= '1';
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epoch_alarm <= '1';
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end if;
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end if;
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epoch_alarm_q <= epoch_alarm;
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epoch_alarm_q <= epoch_alarm;
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-- Fire on rising edge of epoch_alarm
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-- Fire on rising edge of epoch_alarm
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